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small fixes to enable the reuse of the pass manager across multiple modules
[oota-llvm.git]
/
lib
/
CodeGen
/
MachineScheduler.cpp
2012-12-18
Andrew Trick
MISched: Cleanup, redundant statement.
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2012-12-18
Andrew Trick
MISched: Heuristics, compare latency more precisely...
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2012-12-18
Andrew Trick
MISched: Remove SchedRemainder::IsResourceLimited....
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2012-12-18
Andrew Trick
MISched: cleanup, use the proper iterator type.
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2012-12-18
Andrew Trick
MISched: minor improvement, initialize remaining resour...
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2012-12-03
Chandler Carruth
Use the new script to sort the includes of every file...
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2012-12-01
Andrew Trick
misched: Fix RegisterPressureTracker handling of DebugVals.
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2012-12-01
Andrew Trick
misched: fix RegionBegin when DebugValues get shuffled...
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2012-11-29
Benjamin Kramer
misched: Recompute priority queue when DFSResults are...
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2012-11-28
Andrew Trick
misched: Analysis that partitions the DAG into subtrees.
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2012-11-28
Andrew Trick
misched: rename ScheduleDAGILP to ScheduleDFS to prepar...
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2012-11-28
Andrew Trick
misched: Debug output fix. Use an always valid iterator.
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2012-11-13
Andrew Trick
misched: Allow subtargets to enable misched and depende...
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2012-11-12
Andrew Trick
misched: rename interfaceto avoid gcc warnings
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2012-11-12
Andrew Trick
misched: Target-independent support for MacroFusion.
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2012-11-12
Andrew Trick
misched: Target-independent support for load/store...
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2012-11-12
Andrew Trick
misched: Infrastructure for weak DAG edges.
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2012-11-09
Benjamin Kramer
Silence GCC warning about falling off the end of a...
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2012-11-07
Andrew Trick
misched: Heuristics based on the machine model.
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2012-11-06
Andrew Trick
misched: Rename RemainingCount to avoid confusion with...
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2012-10-16
Andrew Trick
misched: Added handleMove support for updating all...
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2012-10-15
Andrew Trick
misched: ILP scheduler for experimental heuristics.
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2012-10-10
Andrew Trick
misched: Use the TargetSchedModel interface wherever...
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2012-10-08
Andrew Trick
misched: avoid scheduling an instruction twice.
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2012-09-14
Andrew Trick
misched: add a hook for custom DAG postprocessing.
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2012-09-11
Manman Ren
Release build: guard dump functions with
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2012-09-11
Andrew Trick
Reorganize MachineScheduler interfaces and publish...
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2012-09-06
Manman Ren
Release build: guard dump functions with "ifndef NDEBUG"
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2012-08-23
Andrew Trick
Simplify the computeOperandLatency API.
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2012-08-22
Craig Topper
Add a getName function to MachineFunction. Use it in...
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2012-07-23
Sylvestre Ledru
Fix a typo (the the => the)
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2012-07-07
Andrew Trick
I'm introducing a new machine model to simultaneously...
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2012-07-02
Andrew Trick
misched: allow NULL InstrItineraries.
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2012-06-29
Andrew Trick
misched: avoid scheduling instructions that can't be...
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2012-06-29
Andrew Trick
misched: count micro-ops toward the issue limit.
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2012-06-16
Benjamin Kramer
Guard private fields that are unused in Release builds...
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2012-06-06
Andrew Trick
Move RegisterClassInfo.h.
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2012-06-06
Andrew Trick
Move RegisterPressure.h.
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2012-06-05
Andrew Trick
misched: API for minimum vs. expected latency.
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2012-06-05
Andrew Trick
misched: comments from code review.
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2012-05-25
Andrew Trick
misched: trace formatting
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2012-05-24
Kaelyn Uhrain
Silence unused variable warnings from when assertions...
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2012-05-24
Andrew Trick
misched: Use the same scheduling heuristics with -misch...
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2012-05-24
Andrew Trick
misched: Trace regpressure.
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2012-05-24
Andrew Trick
misched: Give each ReadyQ a unique ID
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2012-05-24
Andrew Trick
misched: Added ScoreboardHazardRecognizer.
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2012-05-24
Andrew Trick
misched: Release bottom roots in reverse order.
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2012-05-24
Andrew Trick
misched: rename ReadyQ class
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2012-05-24
Andrew Trick
misched: copy comments so compareRPDelta is readable...
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2012-05-17
Andrew Trick
comments
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2012-05-17
Andrew Trick
misched: trace ReadyQ.
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2012-05-17
Andrew Trick
misched: Added 3-level regpressure back-off.
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2012-05-17
Andrew Trick
comment
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2012-05-17
Andrew Trick
misched: fix liveness iterators
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2012-05-10
Andrew Trick
misched: Print machineinstrs with -debug-only=misched
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2012-05-10
Andrew Trick
misched: tracing register pressure heuristics.
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2012-05-10
Andrew Trick
misched: Add register pressure backoff to ConvergingSch...
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2012-05-10
Andrew Trick
misched: Release only unscheduled nodes into ReadyQ.
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2012-05-10
Andrew Trick
misched: Added ReadyQ container wrapper for Top and...
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2012-05-10
Andrew Trick
misched: Introducing Top and Bottom register pressure...
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2012-04-24
Andrew Trick
Fix a naughty header include that breaks "installed...
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2012-04-24
Andrew Trick
misched: try (not too hard) to place debug values where...
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2012-04-24
Andrew Trick
misched: ignore debug values during scheduling
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2012-04-24
Andrew Trick
misched: DAG builder support for tracking register...
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2012-04-01
Andrew Trick
misched: Add finalizeScheduler to complete the target...
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2012-03-21
Andrew Trick
misched: trace LiveIntervals after scheduling.
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2012-03-21
Andrew Trick
misched: obvious iterator update fixes for bottom-up.
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2012-03-21
Andrew Trick
misched: cleanup main loop
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2012-03-19
Lang Hames
Add an option to the MI scheduler to cut off scheduling...
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2012-03-14
Benjamin Kramer
Silence operator precedence warnings.
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2012-03-14
Andrew Trick
misched: implemented a framework for top-down or bottom...
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2012-03-14
Andrew Trick
misched comments
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2012-03-09
Andrew Trick
misched: handle scheduler that insert instructions...
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2012-03-09
Andrew Trick
misched: handle scheduling region boundaries nicely.
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2012-03-09
Andrew Trick
misched interface: rename Begin/End to RegionBegin...
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2012-03-09
Andrew Trick
misched comments
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2012-03-09
Andrew Trick
revert 152356: verify misched changes using -misched...
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2012-03-09
Andrew Trick
misched: allow the default scheduler to be one chosen...
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2012-03-09
Evan Cheng
Cache MBB->begin. It's possible the scheduler / bundler...
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2012-03-08
Andrew Trick
misched interface: Expose the MachineScheduler pass.
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2012-03-07
Andrew Trick
misched prep: Expose the ScheduleDAGInstrs interface...
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2012-03-07
Andrew Trick
misched prep: rename InsertPos to End.
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2012-03-07
Andrew Trick
misched preparation: rename core scheduler methods...
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2012-03-07
Andrew Trick
misched preparation: clarify ScheduleDAG and ScheduleDA...
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2012-03-07
Andrew Trick
Added -view-misched=dags options.
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2012-03-07
Andrew Trick
misched: Use the StartBlock/FinishBlock hooks
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2012-02-22
Andrew Trick
Initialize SUnits before DAG building.
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2012-02-17
Lang Hames
MachineScheduler shouldn't use/preserve LiveDebugVariables.
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2012-02-15
Lang Hames
Disentangle moving a machine instr from updating LiveIn...
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2012-02-10
Andrew Trick
RegAlloc superpass: includes phi elimination, coalescin...
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2012-02-09
Andrew Trick
comment
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2012-02-08
Andrew Trick
misched: bug in debug output.
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2012-02-08
Andrew Trick
stale comment
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2012-01-27
Lang Hames
Add a "moveInstr" method to LiveIntervals. This can...
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2012-01-17
Andrew Trick
misched: Inital interface and implementation for Schedu...
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2012-01-17
Andrew Trick
Renamed MachineScheduler to ScheduleTopDownLive.
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2012-01-14
Andrew Trick
misched: Initial code for building an MI level scheduli...
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2012-01-14
Andrew Trick
misched: Added ScheduleDAGInstrs::IsPostRA
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2012-01-14
Andrew Trick
misched: Invoke the DAG builder on each sequence of...
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2012-01-14
Andrew Trick
Move things around to make the file navigable, even...
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