Expose isXxxConstant() functions from SelectionDAGNodes.h (NFC)
[oota-llvm.git] / lib / Target / AMDGPU /
2015-11-25 Artyom SkrobovExpose isXxxConstant() functions from SelectionDAGNodes...
2015-11-24 Matt ArsenaultAMDGPU: Split LDS vector loads
2015-11-24 Matt ArsenaultAMDGPU: Split x8 and x16 vector loads instead of scalarize
2015-11-19 Pete CooperRevert "Change memcpy/memset/memmove to have dest and...
2015-11-18 Pete CooperChange memcpy/memset/memmove to have dest and source...
2015-11-14 Akira HatanakaReduce the size of MCRelaxableFragment.
2015-11-14 Akira Hatanaka[MCTargetAsmParser] Move the member varialbes that...
2015-11-13 Tom StellardAMDGPU: Add stony support
2015-11-12 Tom StellardRevert "Remove unnecessary call to getAllocatableRegClass"
2015-11-11 Matt ArsenaultAMDGPU: Print more fields in comments
2015-11-11 Matt ArsenaultAMDGPU: Remove dead code
2015-11-11 Matt ArsenaultAMDGPU: Set isAllocatable = 0 on VS_32/VS_64
2015-11-06 Tom StellardAMDGPU/SI: Refactor VOP[12C] tablegen definitions
2015-11-06 Matt ArsenaultAMDGPU: Cleanup includes
2015-11-06 Matt ArsenaultAMDGPU: Create emergency stack slots during frame lowering
2015-11-06 Matt ArsenaultAMDGPU: Remove unused scratch resource operands
2015-11-06 Matt ArsenaultAMDGPU: Add pass to detect used kernel features
2015-11-06 Matt ArsenaultAMDGPU: Fix hardcoded alignment of spill.
2015-11-06 Matt ArsenaultAMDGPU: Hack for VS_32 register pressure
2015-11-06 Tom StellardAMDGPU/SI: Emit HSA kernels with symbol type STT_AMDGPU...
2015-11-05 Matt ArsenaultAMDGPU: Also track whether SGPRs were spilled
2015-11-05 Matt ArsenaultAMDGPU: Print number user SGPRs
2015-11-05 Matt ArsenaultAMDGPU: Disallow s[102:103] on VI in assembler
2015-11-05 Matt ArsenaultAMDGPU: Fix assert when legalizing atomic operands
2015-11-05 Matt ArsenaultAMDGPU: Make addr64 atomic operand order consistent
2015-11-05 Matt ArsenaultAMDGPU: Fix typo
2015-11-03 Matt ArsenaultAMDGPU: Make flat_scratch name consistent
2015-11-03 Matt ArsenaultAMDGPU: Fix asserts on invalid register ranges
2015-11-03 Matt ArsenaultAMDGPU: Fix off by one error in register parsing
2015-11-03 Matt ArsenaultAMDGPU: s[102:103] is unavailable on VI
2015-11-03 Matt ArsenaultAMDGPU: Define correct number of SGPRs
2015-11-03 Matt ArsenaultAMDGPU: Make findUsedSGPR more readable
2015-11-03 Matt ArsenaultAMDGPU: Initialize SIFixSGPRCopies so -print-after...
2015-11-03 Matt ArsenaultAMDGPU: Alphabetize includes
2015-11-03 Matthias BraunScheduleDAGInstrs: Remove IsPostRA flag; NFC
2015-11-02 Matt ArsenaultAMDGPU: Stop assuming vreg for build_vector
2015-11-02 Matt ArsenaultAMDGPU: Error on graphics shaders with HSA
2015-11-02 Matt ArsenaultAMDGPU: Distribute SGPR->VGPR copies of REG_SEQUENCE
2015-10-29 Marek OlsakAMDGPU/SI: handle undef for llvm.SI.packf16
2015-10-29 Marek OlsakAMDGPU/SI: use S_OR for fneg (fabs f32)
2015-10-29 Marek OlsakAMDGPU/SI: use S_AND for i1 trunc
2015-10-24 Matt ArsenaultAMDGPU: Print modifiers when dumping AMDGPUOperand
2015-10-23 Matt ArsenaultAMDGPU: Fix parsing of 32-bit literals with sign bit set
2015-10-21 Matt ArsenaultAMDGPU: Fix adding redundant m0 uses
2015-10-21 Matt ArsenaultAMDGPU: Fix verifier error in SIFoldOperands
2015-10-21 Matt ArsenaultAMDGPU: Split DiagnosticInfoUnsupported into its own...
2015-10-21 Matt ArsenaultAMDGPU: Simplify VOP3 operand legalization.
2015-10-21 Matt ArsenaultAMDGPU: Fix not checking implicit operands in verifyIns...
2015-10-20 Matt ArsenaultAMDGPU: Add MachineInstr overloads for instruction...
2015-10-20 Matt ArsenaultAMDGPU: Stop reserving v[254:255]
2015-10-18 Craig TopperMake a bunch of static arrays const.
2015-10-15 Artyom SkrobovDon't pretend AMDGPU backend knows how to custom-lower...
2015-10-13 Duncan P. N. Exon... AMDGPU: Remove implicit ilist iterator conversions...
2015-10-13 Matt ArsenaultAMDGPU: Refactor isVGPRToSGPRCopy
2015-10-12 Matt ArsenaultDAGCombiner: Combine extract_vector_elt from build_vector
2015-10-12 Matt ArsenaultAMDGPU: Register some more passes so -print-before...
2015-10-08 Justin BognerCodeGen: print and verify after TargetPassConfig::inser...
2015-10-07 Matt ArsenaultAMDGPU: Fix missing implicit m0 uses on movrel instructions
2015-10-07 Matt ArsenaultAMDGPU: Add comment for VOP2b operand class
2015-10-07 Matt ArsenaultAMDGPU: Properly register passes
2015-10-07 Matt ArsenaultAMDGPU: Use explicit register size indirect pseudos
2015-10-07 Matt ArsenaultAMDGPU: Remove inferRegClassFromUses / inferRegClassFro...
2015-10-06 Tom StellardAMDGPU/SI: Remove calling convention assertion from...
2015-10-06 Tom StellardAMDGPU/SI: Add 64-bit versions of v_nop and v_clrexcp
2015-10-05 Tom StellardAMDGPU/SI: Add a helper for creating aliases for the...
2015-10-03 Tom StellardAMDGPU/SI: Remove unused tablegen multiclass
2015-10-02 Matt ArsenaultAMDGPU/SI: Add verifier check for exec reads
2015-10-01 Matt ArsenaultAMDGPU: Fix unused variable warning in release build
2015-10-01 Matt ArsenaultAMDGPU: Move SIFixSGPRLiveRanges to be a regalloc pass
2015-10-01 Matt ArsenaultAMDGPU: Merge if and switch
2015-10-01 Matt ArsenaultAMDGPU: Remove dead code
2015-10-01 Matt ArsenaultAMDGPU: Make SIInsertWaits about a factor of 4 faster
2015-10-01 Tom StellardAMDGPU/SI: Remove assert from AMDGPUOpenCLImageTypeLowe...
2015-10-01 Tom StellardAMDGPU: Add MEM_RAT STORE_TYPED.
2015-10-01 Tom StellardAMDGPU: Factor out EOP query.
2015-10-01 Tom StellardAMDGPU/SI: Re-order PreloadedValue enum and number...
2015-09-29 Marek OlsakAMDGPU/SI: Don't set DATA_FORMAT if ADD_TID_ENABLE...
2015-09-28 Matt ArsenaultAMDGPU: Factor switch into separate function
2015-09-28 Matt ArsenaultAMDGPU: Fix splitting x16 SMRD loads
2015-09-28 Matt ArsenaultAMDGPU: Fix moving SMRD loads with literal offsets...
2015-09-28 Matt ArsenaultAMDGPU: Fix splitting SMRD with large offset
2015-09-28 Andrew KaylorImproved the interface of methods commuting operands...
2015-09-26 Matt ArsenaultAMDGPU: Remove hasPostISelHook from most instructions
2015-09-26 Matt ArsenaultAMDGPU: Switch over reg class size instead of checking...
2015-09-26 Matt ArsenaultAMDGPU: Don't handle invalid reg classes in helper...
2015-09-26 Saleem AbdulrasoolAMDGPU: address -Winconsistent-missing-override
2015-09-26 Matt ArsenaultAMDGPU: Set CopyCost of register classes
2015-09-26 Matt ArsenaultAMDGPU: VOP3b definition cleanups
2015-09-26 Matt ArsenaultAMDGPU: Fix sched model for VOP2b instructions
2015-09-25 Matt ArsenaultAMDGPU: Construct new buffer instruction when moving...
2015-09-25 Tom StellardAMDGPU/SI: Use .hsatext section instead of .text for HSA
2015-09-25 Matt ArsenaultAMDGPU: Make getNamedOperandIdx declaration readonly
2015-09-25 Matt ArsenaultAMDGPU: Disable some passes that are not meaningful
2015-09-25 Matt ArsenaultAMDGPU: Handle i64->v2i32 loads/stores in PreprocessISelDAG
2015-09-25 Matt ArsenaultAMDGPU: Fix recomputing dominator tree unnecessarily
2015-09-25 Matt ArsenaultAMDGPU: Re-justify workaround and fix worked around...
2015-09-25 Matt ArsenaultAMDGPU: Don't create REG_SEQUENCE with SGPR dest and...
2015-09-25 Matt ArsenaultAMDGPU: Fix not adding exec to defs of cmpx instruction...
2015-09-25 Matt ArsenaultAMDGPU: Improve accuracy of instruction rates for VOPC
2015-09-25 Matt ArsenaultAMDGPU: Remove unused includes
next