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This patch introduces A15 as a target in LLVM.
[oota-llvm.git]
/
lib
/
Target
/
ARM
/
ARMInstrNEON.td
2011-12-08
Jim Grosbach
ARM NEON two-operand aliases for VSHL(register).
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2011-12-08
Jim Grosbach
Fix copy/past-o.
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2011-12-08
Jim Grosbach
ARM NEON two-operand aliases for VMUL.
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2011-12-08
Jim Grosbach
ARM optional destination operand variants for VEXT...
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2011-12-07
Jim Grosbach
ARM two-operand aliases for VAND/VEOR/VORR instructions.
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2011-12-07
Jim Grosbach
ARM two-operand aliases for VADDW instructions.
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2011-12-07
Jim Grosbach
ARM two-operand aliases for VADD instructions.
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2011-12-07
Jim Grosbach
ARM NEON VCLT(register) is a pseudo aliasing VCGT(regis...
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2011-12-07
Jim Grosbach
ARM tidy up and remove no longer needed InstAlias defin...
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2011-12-07
Jim Grosbach
ARM: NEON SHLL instruction immediate operand range...
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2011-12-07
Jim Grosbach
ARM: Parameterize the immediate operand type for NEON...
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2011-12-05
Jim Grosbach
ARM assembly parsing for the rest of the VMUL data...
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2011-12-05
Jim Grosbach
Fix previous commit. Oops.
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2011-12-05
Jim Grosbach
Tidy up. No functional change.
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2011-12-05
Jim Grosbach
ARM assmebler parsing for two-operand VMUL instructions.
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2011-12-02
Jim Grosbach
ARM NEON VEXT aliases for data type suffices.
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2011-12-02
Jim Grosbach
ARM VEXT tighten up operand classes a bit.
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2011-12-02
Jim Grosbach
ARM VST1 single lane assembly parsing.
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2011-12-02
Jim Grosbach
ARM VLD1 single lane assembly parsing.
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2011-12-02
Jim Grosbach
Clean up aliases for ARM VLD1 single-lane assembly...
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2011-12-02
Jim Grosbach
ARM start parsing VLD1 single lane instructions.
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2011-11-30
Jim Grosbach
ARM parsing for VLD1 all lanes, with writeback.
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2011-11-30
Jim Grosbach
ARM parsing for VLD1 two register all lanes, no writeback.
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2011-11-30
Jim Grosbach
ARM parsing aliases for VLD1 single register all lanes.
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2011-11-29
Jim Grosbach
Tidy up a bit.
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2011-11-29
Jim Grosbach
Add comment.
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2011-11-29
Jim Grosbach
ARM parsing aliases for data-size suffices on VST1.
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2011-11-29
Jim Grosbach
ARM assembly parsing and encoding for four-register...
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2011-11-29
Jim Grosbach
ARM assembly parsing and encoding for three-register...
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2011-11-15
Jim Grosbach
ARM assembly parsing for data type suffices on NEON...
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2011-11-15
Jim Grosbach
ARM alternate size suffices for VTRN instructions.
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2011-11-15
Owen Anderson
Fix an ambiguous decoding where we failed to properly...
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2011-11-15
Jim Grosbach
ARM parsing datatype suffix variants for register-write...
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2011-11-15
Evan Cheng
Add vmov.f32 to materialize f32 immediate splats which...
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2011-11-15
Jim Grosbach
ARM parsing datatype suffix variants for fixed-writebac...
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2011-11-14
Jim Grosbach
ARM parsing datatype suffix variants for non-writeback...
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2011-11-14
Jim Grosbach
ARM parsing datatype suffix variants for non-writeback...
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2011-11-14
Jim Grosbach
Add explanatory comment.
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2011-11-14
Jim Grosbach
ARM parsing optional datatype suffix for VAND/VEOR...
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2011-11-12
Jim Grosbach
Re-apply 144430, this time with the associated isel...
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2011-11-11
Jim Grosbach
Oops. Missed the isel half of this. revert while I...
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2011-11-11
Jim Grosbach
ARM assembly parsing for VST1 two-register encoding.
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2011-10-31
Jim Grosbach
ARM VST1 w/ writeback assembly parsing and encoding.
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2011-10-28
Owen Anderson
Specify that the high bit of the alignment field is...
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2011-10-25
Jim Grosbach
ARM assembly parsing and encoding for VLD1 with writeback.
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2011-10-24
Jim Grosbach
Nuke dead code. Nothing generates the VLD1d64QPseudo_UP...
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2011-10-24
Jim Grosbach
ARM assembly parsing and encoding for VLD1 w/ writeback.
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2011-10-24
Jim Grosbach
ARM assembly parsing and encoding for VLD1 w/ writeback.
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2011-10-24
Jim Grosbach
ARM refactor am6offset usage for VLD1.
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2011-10-21
Jim Grosbach
Assembly parsing for 4-register sequential variant...
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2011-10-21
Jim Grosbach
Assembly parsing for 2-register sequential variant...
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2011-10-21
Jim Grosbach
Assembly parsing for 4-register variant of VLD1.
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2011-10-21
Jim Grosbach
Assembly parsing for 3-register variant of VLD1.
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2011-10-21
Jim Grosbach
ARM VLD parsing and encoding.
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2011-10-21
Jim Grosbach
Remove some outdated comments.
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2011-10-20
Jim Grosbach
ARM VLD1/VST1 (one register, no writeback) assembly...
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2011-10-20
Jim Grosbach
ARM VTBX (one register) assembly parsing and encoding.
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2011-10-18
Jim Grosbach
ARM VTBL (one register) assembly parsing and encoding.
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2011-10-18
Jim Grosbach
Yet more ARM NEON assembly parsing for the lane index...
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2011-10-18
Jim Grosbach
ARM vmla/vmls assembly parsing for the lane index operand.
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2011-10-18
Jim Grosbach
ARM vmov assembly parsing for the lane index operand.
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2011-10-18
Jim Grosbach
ARM vmla/vmls assembly parsing for the lane index operand.
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2011-10-18
Jim Grosbach
ARM vqdmulh assembly parsing for the lane index operand.
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2011-10-18
Jim Grosbach
ARM vmul assembly parsing for the lane index operand.
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2011-10-18
Jim Grosbach
ARM vqdmlal assembly parsing for the lane index operand.
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2011-10-18
Jim Grosbach
ARM assembly parsing and encoding for VMOV.i64.
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2011-10-18
Jim Grosbach
ARM assembly parsing and encoding for VMOV/VMVN/VORR...
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2011-10-17
Jim Grosbach
ARM assembly parsing and encoding for VMOV/VMVN/VORR...
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2011-10-17
Jim Grosbach
ARM NEON "vmov.i8" immediate assembly parsing and encoding.
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2011-10-17
Jim Grosbach
Tidy up organization.
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2011-10-07
Jim Grosbach
ARM NEON assembly parsing and encoding for VDUP(scalar).
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2011-08-20
Chad Rosier
Remove the VMOVQQ pseudo instruction.
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2011-08-20
Chad Rosier
Remove VMOVQQQQ pseudo instruction.
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2011-08-15
Owen Anderson
Specify a necessary fixed bit for VLD3DUP, and otherwis...
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2011-08-15
Owen Anderson
Fix problems decoding the to/from-lane NEON memory...
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2011-08-09
Owen Anderson
Replace the existing ARM disassembler with a new one...
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2011-08-05
Bob Wilson
Add missing register constraint for some VLD3/VLD4...
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2011-07-15
Owen Anderson
Remove VMOVDneon and VMOVQ, which are just aliases...
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2011-07-15
Owen Anderson
Remove unnecessary duplicate instruction definitions...
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2011-06-13
Jim Grosbach
Clean up a few 80 column violations.
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2011-06-02
Tanya Lattner
Fix encoding for VEXTdf.
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2011-05-09
Mon P Wang
Fixed MC encoding for index_align for VLD1/VST1 (single...
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2011-04-07
Mon P Wang
Fixed encoding for VEXTqf
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2011-03-30
Owen Anderson
Somehow we managed to forget to encode the lane index...
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2011-03-30
Cameron Zwarich
Add a ARM-specific SD node for VBSL so that forms with...
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2011-03-29
Owen Anderson
Get rid of the non-writeback versions VLDMDB and VSTMDB...
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2011-03-11
Jim Grosbach
ARM VDUPfd and VDUPfq can just be patterns. The instruc...
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2011-03-11
Jim Grosbach
ARM VDUPLNfq and VDUPLNfd definitions can just be Pat...
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2011-03-11
Jim Grosbach
ARM VREV64df and VREV64qf can just be patterns. The...
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2011-03-09
Bill Wendling
* Correct encoding for VSRI.
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2011-03-09
Bill Wendling
Correct the encoding for VRSRA and VSRA instructions.
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2011-03-08
Bill Wendling
* Fix VRSHR and VSHR to have the correct encoding for...
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2011-03-07
Bill Wendling
Rename the narrow shift right immediate operands to...
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2011-03-01
Bill Wendling
Narrow right shifts need to encode their immediates...
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2011-02-25
Bob Wilson
Add patterns to use post-increment addressing for Neon...
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2011-02-07
Bob Wilson
Change VLD3/4 and VST3/4 for quad registers to not...
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2011-02-07
Bob Wilson
Fix some NEON instruction itineraries.
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2011-01-07
Bob Wilson
Add ARM patterns to match EXTRACT_SUBVECTOR nodes.
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2010-12-18
Bob Wilson
Rearrange some Neon multiclasses. No functional changes.
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2010-12-18
Bob Wilson
Fix result type of Neon floating-point comparisons...
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