[Modules] Make Support/Debug.h modular. This requires it to not change
[oota-llvm.git] / lib / Target / ARM / ARMInstrThumb.td
2014-01-13 Tim NorthoverARM: constrain Thumb LDRLIT pseudo-instructions to...
2014-01-06 Tim NorthoverARM MachO: sort out isTargetDarwin/isTargetIOS/......
2013-12-23 Saleem AbdulrasoolARM: bkpt has an implicit immediate constant 0
2013-12-02 Tim NorthoverARM: add pseudo-instructions for lit-pool global materi...
2013-11-25 Tim NorthoverARM: remove unused patterns.
2013-10-23 Artyom SkrobovMake ARM hint ranges consistent, and add tests for...
2013-10-18 Richard BartonAdd hint disassembly syntax for 16-bit Thumb hint instr...
2013-10-07 Tim NorthoverARM: allow cortex-m0 to use hint instructions
2013-10-03 Amara Emerson[ARM] Warn on deprecated IT blocks in v8 AArch32 assembly.
2013-10-01 Joey Gouly[ARM] Introduce the 'sevl' instruction in ARMv8.
2013-09-05 Richard BartonAdd AArch32 DCPS{1,2,3} and HLT instructions.
2013-08-22 Tim NorthoverARM: use TableGen patterns to select CMOV operations.
2013-08-15 Mihai PopaThis fixes three issues related to Thumb literal loads:
2013-08-09 Mihai PopaFix assembling of Thumb2 branch instructions.
2013-07-22 Mihai PopaThis adds range checking for "ldr Rn, [pc, #imm]" Thumb
2013-07-03 Mihai PopaThis corrects the implementation of Thumb ADR instruct...
2013-06-06 Arnold SchwaighoferARM sched model: Add branch thumb instructions
2013-06-06 Arnold SchwaighoferARM sched model: Add more ALU and CMP thumb instructions
2013-06-04 Arnold SchwaighoferRevert series of sched model patches until I figure...
2013-06-04 Arnold SchwaighoferARM sched model: Add branch thumb instructions
2013-06-04 Arnold SchwaighoferARM sched model: Add more ALU and CMP thumb instructions
2012-11-06 Chad RosierMark the Int_eh_sjlj_dispatchsetup pseudo instruction...
2012-10-30 Jim GrosbachARM: Better disassembly for pc-relative LDR.
2012-09-27 Sylvestre LedruRevert 'Fix a typo 'iff' => 'if''. iff is an abreviatio...
2012-09-27 Sylvestre LedruFix a typo 'iff' => 'if'
2012-08-28 Jakob Stoklund OlesenRevert r162713: "Add ATOMIC_LDR* pseudo-instructions...
2012-08-27 Jakob Stoklund OlesenAdd ATOMIC_LDR* pseudo-instructions to model atomic_loa...
2012-08-24 Jakob Stoklund OlesenMissed tLEApcrelJT.
2012-07-13 Jakob Stoklund OlesenRemove variable_ops from ARM call instructions.
2012-06-23 Evan Cheng(sub X, imm) gets canonicalized to (add X, -imm)
2012-06-02 Benjamin KramerFix typos found by github.com/lyda/misspell-check
2012-05-03 Kevin EnderbyFix issues with the ARM bl and blx thumb instructions...
2012-05-02 Richard BartonDisallow YIELD and other allocated nop hints in pre...
2012-04-27 Jim GrosbachARM: Thumb add(sp plus register) asm constraints.
2012-04-27 Jim GrosbachARM: Tweak tADDrSP definition for consistent operand...
2012-04-11 Jim GrosbachARM add missing Thumb1 two-operand aliases for shift...
2012-04-06 Jakob Stoklund OlesenEliminate iOS-specific tail call instructions.
2012-04-06 Jakob Stoklund OlesenDeduplicate ARM call-related instructions.
2012-04-05 Jim GrosbachARM assembly aliases for add negative immediates using...
2012-02-24 Jakob Stoklund OlesenSwitch ARM target to register masks.
2012-02-18 Jia LiuEmacs-tag and some comment fix for all ARM, CellSPU...
2012-02-09 James MolloyTeach the MC and disassembler about SoftFail, and hook...
2012-01-18 Jim GrosbachRename pattern for clarity.
2012-01-13 Jakob Stoklund OlesenUse RegisterTuples to generate pseudo-registers.
2011-12-22 Bob WilsonAdd variants of the dispatchsetup pseudo for Thumb...
2011-12-20 Evan ChengARM target code clean up. Check for iOS, not Darwin...
2011-12-13 Jim GrosbachARM pre-UAL NEG mnemonic for convenience when porting...
2011-10-17 Bill WendlingNow Igor, throw the switch...give my creation life!
2011-10-15 Jakob Stoklund OlesenMark tADDrSPi as having side effects again.
2011-10-14 Jakob Stoklund OlesenBan rematerializable instructions with side effects.
2011-09-20 Jim GrosbachThumb1 convenience aliases for disassembler round-trip...
2011-09-20 Jim GrosbachThumb CPS definition is not disassembler only.
2011-09-16 Jim GrosbachThumb2 assembly parsing and encoding for SUB(immediate).
2011-09-15 Eli FriedmanUse a more efficient lowering for Unordered/Monotonic...
2011-09-09 Owen AndersonThumb unconditional branches are allowed in IT blocks...
2011-08-24 Jim GrosbachThumb parsing and encoding for SUB (SP minu immediate).
2011-08-24 Jim GrosbachThumb parsing and encoding support for ADD SP instructions.
2011-08-24 Jim GrosbachAdd missing explicit writeback operand to tSTMIA_UPD.
2011-08-24 Jim GrosbachThumb add SP assembly syntax fix.
2011-08-24 Jim GrosbachThumb1 ADD/SUB SP instructions are predicable in Thumb2...
2011-08-23 Jim GrosbachThumb parsing and encoding for SVC.
2011-08-23 Jim GrosbachThumb parsing and encoding for tSTRspi.
2011-08-23 Jim GrosbachClean up Thumb load/store multiple definitions.
2011-08-22 Jim GrosbachRevert r138278 now that r138289 has fixed the root...
2011-08-22 Jim GrosbachTemporarilly mark tMUL as not commutable.
2011-08-22 Jim GrosbachClean up predicates on ARM target instruction aliases.
2011-08-19 Jim GrosbachThumb parsing and encoding support for NOP.
2011-08-19 Jim GrosbachFix NEG alias
2011-08-19 Jim GrosbachUpdate tests.
2011-08-19 Jim GrosbachThumb assembly parsing and encoding for MUL.
2011-08-19 Jim GrosbachThumb assembly parsing and encoding for MOV.
2011-08-19 Jim GrosbachThumb assembly parsing and encoding for LSL(immediate).
2011-08-19 Jim GrosbachThumb assembly parsing and encoding for LDRSB and LDRSH.
2011-08-19 Jim GrosbachThumb assembly parsing and encoding for LDRH.
2011-08-19 Jim GrosbachThumb assembly parsing and encoding for LDRB.
2011-08-19 Jim GrosbachThumb assembly parsing and encoding for LDR(immediate...
2011-08-19 Jim GrosbachThumb assembly parsing and encoding for LDR(immediate...
2011-08-19 Jim GrosbachAdd explanatory comment.
2011-08-18 Jim GrosbachThumb assembly parsing and encoding for LDM instruction.
2011-08-18 Jim GrosbachThumb assembly parsing and encoding for CMP.
2011-08-18 Jim GrosbachThumb instructions CBZ and CBNZ are Thumb2, not THumb1.
2011-08-18 Jim Grosbach80 columns.
2011-08-17 Jim GrosbachClean up patterns for Thumb1 system instructions.
2011-08-17 Jim GrosbachARM clean up the imm_sr operand class representation.
2011-08-17 Jim GrosbachThumb assembly parsing and encoding for ADR.
2011-08-16 Jim GrosbachThumb ADD(immediate) parsing support.
2011-08-15 Owen AndersonFix decoding LDRSB and LDRSH in Thumb1 mode. Patch...
2011-08-09 Owen AndersonReplace the existing ARM disassembler with a new one...
2011-08-08 Owen AndersonThumb1 BL instructions encoding 22 bits of displacement...
2011-08-08 Owen AndersonFix encodings for Thumb ASR and LSR immediate operands...
2011-08-03 Jim GrosbachARM refactoring assembly parsing of memory address...
2011-08-03 Owen AndersonFix broken encoding of tCBNZ.
2011-08-01 Jim GrosbachMove imm0_255 to ARMInstrInfo.td with the other immedia...
2011-07-26 Jim GrosbachARM parsing and encoding for SVC instruction.
2011-07-22 Jim GrosbachThumb assembly support for SETEND instruction.
2011-07-18 Owen AndersonRevamp our handling of tLDMIA[_UPD] and tSTMIA[_UPD...
2011-07-18 Owen AndersonMark the Darwin assembler workout as isCodeGenOnly...
2011-07-18 Owen AndersonRe-apply r135319 with a fix for the constant island...
2011-07-16 Owen AndersonRevert r135319 in an attempt to get to unbreak testers.
2011-07-15 Owen AndersonGet rid of the separate opcodes for the Darwin versions...
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