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Make $fp and $ra callee-saved registers and let PrologEpilogInserter handle
[oota-llvm.git]
/
lib
/
Target
/
ARM
/
ARMSchedule.td
2011-01-20
Evan Cheng
Sorry, several patches in one.
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2010-11-30
Bob Wilson
Add support for NEON VLD3-dup instructions.
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2010-11-29
Bob Wilson
Add support for NEON VLD3-dup instructions.
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2010-11-28
Bob Wilson
Add support for NEON VLD2-dup instructions.
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2010-11-27
Bob Wilson
Add NEON VLD1-dup instructions (load 1 element to all...
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2010-11-13
Evan Cheng
Conditional moves are slightly more expensive than...
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2010-11-03
Evan Cheng
Fix preload instruction isel. Only v7 supports pli...
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2010-11-02
Bob Wilson
Add NEON VST1-lane instructions. Partial fix for Radar...
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2010-11-01
Bob Wilson
Add NEON VLD1-lane instructions. Partial fix for Radar...
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2010-10-11
Evan Cheng
More ARM scheduling itinerary fixes.
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2010-10-11
Evan Cheng
Proper VST scheduling itineraries.
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2010-10-09
Evan Cheng
Add VLD4 scheduling itineraries.
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2010-10-09
Evan Cheng
Finish vld3 and vld4.
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2010-10-09
Evan Cheng
Correct some load / store instruction itinerary mistakes:
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2010-10-07
Evan Cheng
Model operand cycles of vldm / vstm; also fixes schedul...
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2010-10-06
Evan Cheng
- Add TargetInstrInfo::getOperandLatency() to compute...
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2010-10-01
Evan Cheng
NEON scheduling info fix. vmov reg, reg are single...
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2010-09-30
Evan Cheng
ARM instruction itinerary fixes:
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2010-09-29
Evan Cheng
Model Cortex-a9 load to SUB, RSB, ADD, ADC, SBC, RSC...
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2010-09-29
Evan Cheng
Separate itinerary classes for mvn from mov; for tst...
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2010-09-29
Evan Cheng
Assign bitwise binary instructions different itinerary...
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2010-09-28
Evan Cheng
Add support to model pipeline bypass / forwarding.
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2010-09-25
Evan Cheng
Remove a unused instruction itinerary class.
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2010-09-25
Evan Cheng
Fix zero and sign extension instructions scheduling...
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2010-09-24
Evan Cheng
More pseudo instruction scheduling itinerary fixes.
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2010-09-24
Evan Cheng
Fix scheduling itinerary for pseudo mov immediate instr...
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2010-09-09
Evan Cheng
For each instruction itinerary class, specify the numbe...
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2010-09-08
Evan Cheng
Fix LDM_RET schedule itinery.
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2010-04-18
Anton Korobeynikov
Make processor FUs unique for given itinerary. This...
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2010-04-07
Anton Korobeynikov
Split A8/A9 itins - they already were too big.
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2010-04-07
Anton Korobeynikov
Fix itins for VABA
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2010-04-07
Anton Korobeynikov
VHADD differs from VHSUB at least on A9 - the former...
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2010-04-07
Anton Korobeynikov
Define new itin classes for ARM <-> VFP reg moves to...
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2010-04-07
Anton Korobeynikov
Add new itin classes for FP16 <-> FP32 conversions...
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2010-04-07
Anton Korobeynikov
Make use of new reserved/required scheduling stuff...
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2009-09-25
David Goodwin
Finish scheduling itineraries for NEON.
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2009-09-24
David Goodwin
Make the end-of-itinerary mark explicit. Some cleanup.
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2009-09-23
David Goodwin
Checkpoint NEON scheduling itineraries.
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2009-09-21
David Goodwin
Add Cortex-A8 VFP model.
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2009-08-19
David Goodwin
Update Cortex-A8 instruction itineraries for integer...
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2009-08-15
Evan Cheng
Turn on if-conversion for thumb2.
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2009-08-13
David Goodwin
Finalize itineraries for cortex-a8 integer multiply
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2009-08-11
David Goodwin
Allow a zero cycle stage to reserve/require a FU withou...
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2009-08-10
David Goodwin
Checkpoint scheduling itinerary changes.
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2009-07-21
Evan Cheng
Add fake v7 itineraries for now.
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2009-06-19
Evan Cheng
Latency information for ARM v6. It's rough and not...
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