[Sparc] Delete FPMover Pass and remove Fp* Pseudo-instructions from Sparc backend.
[oota-llvm.git] / lib / Target / ARM /
2013-06-08 Amaury de la VieuvilleARM: fix VMOVvnf32 decoding when ambiguous with VCVT
2013-06-08 Amaury de la VieuvilleARM: enforce SRS decoding constraints
2013-06-08 Amaury de la VieuvilleARM: fix CPS decoding when ambiguous with QADD
2013-06-08 Amaury de la VieuvilleARM: fix VCVT decoding
2013-06-08 JF BastienFix unused variable warning from my previous patch.
2013-06-07 JF BastienARM FastISel integer sext/zext improvements
2013-06-07 Bill WendlingDon't cache the instruction and register info from...
2013-06-07 Arnold SchwaighoferARM sched model: Use the right resources for DIV
2013-06-07 Arnold SchwaighoferARM sched model: Add VFP div instruction on Swift
2013-06-07 Arnold SchwaighoferARM sched model: Add SIMD/VFP load/store instructions...
2013-06-06 Arnold SchwaighoferRevert "ARM sched model: Add SIMD/VFP load/store instru...
2013-06-06 Arnold SchwaighoferARM sched model: Add SIMD/VFP load/store instructions...
2013-06-06 Arnold SchwaighoferARM sched model: Add integer VFP/SIMD instructions...
2013-06-06 Arnold SchwaighoferARM sched model: Add integer load/store instructions...
2013-06-06 Arnold SchwaighoferARM sched model: Add integer arithmetic instructions...
2013-06-06 Arnold SchwaighoferARM sched model: Cortex A9 - More InstRW sched resources
2013-06-06 Arnold SchwaighoferARM sched model: Add branch thumb instructions
2013-06-06 Arnold SchwaighoferARM sched model: Add branch thumb2 instructions
2013-06-06 Arnold SchwaighoferARM sched model: Add branch instructions
2013-06-06 Arnold SchwaighoferARM sched model: Add preload thumb2 instructions
2013-06-06 Arnold SchwaighoferARM sched model: Add preload instructions
2013-06-06 Arnold SchwaighoferARM sched model: Add more ALU and CMP thumb instructions
2013-06-06 Arnold SchwaighoferARM sched model: Add more ALU and CMP thumb2 instructions
2013-06-06 Bill WendlingCache the TargetLowering info object as a pointer.
2013-06-05 Arnold SchwaighoferARM sched model: Add more ALU and CMP instructions
2013-06-05 Arnold SchwaighoferARM sched model: Add divsion, loads, branches, vfp cvt
2013-06-05 Arnold SchwaighoferARMInstrInfo: Improve isSwiftFastImmShift
2013-06-05 Mihai PopaThis is a simple patch that changes RRX and RRXS to...
2013-06-04 Evan ChengCortex-R5 can issue Thumb2 integer division instructions.
2013-06-04 Arnold SchwaighoferRevert series of sched model patches until I figure...
2013-06-04 Arnold SchwaighoferARM sched model: Add VFP div instruction on Swift
2013-06-04 Arnold SchwaighoferARM sched model: Add SIMD/VFP load/store instructions...
2013-06-04 Arnold SchwaighoferARM sched model: Add integer VFP/SIMD instructions...
2013-06-04 Arnold SchwaighoferARM sched model: Add integer load/store instructions...
2013-06-04 Arnold SchwaighoferARM sched model: Add integer arithmetic instructions...
2013-06-04 Arnold SchwaighoferARM sched model: Cortex A9 - More InstRW sched resources
2013-06-04 Arnold SchwaighoferARM sched model: Add branch thumb instructions
2013-06-04 Arnold SchwaighoferARM sched model: Add branch thumb2 instructions
2013-06-04 Arnold SchwaighoferARM sched model: Add branch instructions
2013-06-04 Arnold SchwaighoferARM sched model: Add preload thumb2 instructions
2013-06-04 Arnold SchwaighoferARM sched model: Add preload instructions
2013-06-04 Arnold SchwaighoferARM sched model: Add more ALU and CMP thumb instructions
2013-06-04 Arnold Schwaighofer ARM sched model: Add more ALU and CMP thumb2 instructions
2013-06-04 Arnold SchwaighoferARM sched model: Add more ALU and CMP instructions
2013-06-04 Arnold SchwaighoferARM sched model: Add divsion, loads, branches, vfp cvt
2013-06-04 Arnold SchwaighoferARMInstrInfo: Improve isSwiftFastImmShift
2013-06-04 David MajnemerARM: Fix crash in ARM backend inside of ARMConstantIsla...
2013-05-31 Ahmed BougachaAdd a way to define the bit range covered by a SubRegIndex.
2013-05-31 Tim NorthoverARM: permit upper-case BE/LE on setend instruction
2013-05-31 Tim NorthoverARM: add fstmx and fldmx instructions for assembly
2013-05-31 Tim NorthoverARM: fix VEXT encoding corner case
2013-05-30 Rafael EspindolaRevert r182937 and r182877.
2013-05-29 Andrew TrickOrder CALLSEQ_START and CALLSEQ_END nodes.
2013-05-29 JF BastienEnable FastISel on ARM for Linux and NaCl
2013-05-29 JF BastienTidy some register classes for ARM and Thumb
2013-05-25 Andrew TrickTrack IR ordering of SelectionDAG nodes 2/4.
2013-05-24 Quentin ColombetFollow up of the introduction of MCSymbolizer.
2013-05-24 Michael J. SpencerReplace Count{Leading,Trailing}Zeros_{32,64} with count...
2013-05-24 Benjamin KramerRemove the Copied parameter from MemoryObject::readBytes.
2013-05-24 Ahmed BougachaMC: Disassembled CFG reconstruction.
2013-05-24 Ahmed BougachaAdd MCSymbolizer for symbolic/annotated disassembly.
2013-05-23 Tim NorthoverARM: implement @llvm.readcyclecounter intrinsic
2013-05-23 Tim NorthoverARM: Add Performance Monitor Extensions feature
2013-05-22 Chad RosierSimplify logic now that r182490 is in place. No functi...
2013-05-20 Mihai PopaVSTn instructions have a number of encoding constraints...
2013-05-20 Mihai PopaQ registers are encoded in fields of the same length...
2013-05-20 Stepan DyatkovskiyPR15868 fix.
2013-05-19 Benjamin KramerReplace some bit operations with simpler ones. No funct...
2013-05-18 Matt ArsenaultAdd LLVMContext argument to getSetCCResultType
2013-05-17 JF BastienSupport unaligned load/store on more ARM targets
2013-05-15 Derek SchuffRevert "Support unaligned load/store on more ARM targets"
2013-05-15 Derek SchuffSupport unaligned load/store on more ARM targets
2013-05-14 Arnold SchwaighoferARM ISel: Don't create illegal types during LowerMUL
2013-05-13 Mihai PopaThe purpose of the patch is to fix the syntax of ARM...
2013-05-13 Lang HamesCorrectly preserve the input chain for potential tailca...
2013-05-13 Rafael EspindolaRemove the MachineMove class.
2013-05-10 Rafael EspindolaRemove unused argument.
2013-05-10 Logan ChienImplement AsmParser for ARM unwind directives.
2013-05-08 Stepan DyatkovskiyFor r181148: fixed warning 'enumeral and non-enumeral...
2013-05-05 Evan ChengARM AnalyzeBranch should conservatively return true...
2013-05-05 Stepan DyatkovskiyFor ARM backend, fixed "byval" attribute support.
2013-05-05 Dmitri GribenkoAdd ArrayRef constructor from None, and do the cleanups...
2013-05-03 Amara EmersonRevert r181009.
2013-05-03 Amara EmersonAdd support for reading ARM ELF build attributes.
2013-04-30 Rafael EspindolaText files should not be marked executable.
2013-04-30 Mihai Popas tightens up the encoding description for ARM post...
2013-04-30 Stepan DyatkovskiyRefactoring patch.
2013-04-26 Quentin ColombetARM: Fix encoding of hint instruction for Thumb.
2013-04-26 Benjamin KramerARM/NEON: Pattern match vector integer abs to vabs.
2013-04-25 Arnold SchwaighoferARM cost model: Integer div and rem is lowered to a...
2013-04-23 Stephen LinAdd more tests for r179925 to verify correct handling...
2013-04-23 Stephen LinLowercase "is" boolean variable prefix for consistency...
2013-04-22 Eric ChristopherNo really, don't store anything to this since it's...
2013-04-22 Eric ChristopherRemove variable store that is never read.
2013-04-22 Stepan DyatkovskiyFix for 5.5 Parameter Passing --> Stage C:
2013-04-21 Jim GrosbachLegalize vector truncates by parts rather than just...
2013-04-21 Tim NorthoverARM: Use ldrd/strd to spill 64-bit pairs when available.
2013-04-20 Tim NorthoverARM: don't add FrameIndex offset for LDMIA (has no...
2013-04-20 Tim NorthoverRemove unused ShouldFoldAtomicFences flag.
2013-04-20 Tim NorthoverRemove unused MEMBARRIER DAG node; it's been replaced...
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