Create new accessors to get arguments for call/invoke instructions. It breaks
[oota-llvm.git] / lib / Target / ARM /
2010-06-05 Chris Lattnerrevert r105521, which is breaking the buildbots with...
2010-06-05 Bruno Cardoso LopesInitial AVX support for some instructions. No patterns...
2010-06-05 Dale JohannesenImprovements to tail call code. No functional effect
2010-06-04 Dale JohannesenMore thoroughly disable tails calls by default.
2010-06-04 Jim GrosbachAnother fix to prevent debug info from affecting codege...
2010-06-04 Jim Grosbachmore dbg_value adjustments so debug info doesn't affect...
2010-06-04 Jim Grosbachfix typo
2010-06-04 Bob WilsonFor NEON vectors with 32- or 64-bit elements, select...
2010-06-03 Jim GrosbachTeach the ARM load-store optimizer to deal with dbg_val...
2010-06-03 Dale JohannesenEarly implementation of tail call for ARM.
2010-06-02 Jakob Stoklund OlesenSlightly change the meaning of the reMaterialize target...
2010-06-02 Jim GrosbachClean up 80 column violations. No functional change.
2010-06-02 Rafael EspindolaRemove the TargetRegisterClass member from CalleeSavedInfo
2010-06-02 Bob WilsonRename canCombinedSubRegIndex method to something more...
2010-06-02 Rafael EspindolaReplace ARM's getCalleeSavedRegClasses with a simpler...
2010-05-29 Anton KorobeynikovSome A9 load/store cleanups
2010-05-29 Anton KorobeynikovSome rough approximations for load/stores on A9
2010-05-29 Anton KorobeynikovNEON/VFP stuff can be issued only via Pipe1 on A9
2010-05-29 Anton KorobeynikovAdd some integer instruction itineraries for A9
2010-05-28 Evan ChengSchedule high latency instructions for latency reductio...
2010-05-28 Jim Grosbachcorrect retattr
2010-05-28 Jim GrosbachCosmetic cleanup. No functional change.
2010-05-28 Jim Grosbachmake sure accesses to set up the jmpbuf don't get moved...
2010-05-28 Bob WilsonAdd the cc_out operand for t2RSBrs instructions. I...
2010-05-27 Jim GrosbachUpdate the saved stack pointer in the sjlj function...
2010-05-27 Evan ChengUse report_fatal_error, not llvm_unreachable.
2010-05-27 Jim Grosbachback out 104862/104869. Can reuse stacksave after all...
2010-05-27 Evan Chengllvm can't correctly support 'H', 'Q' and 'R' modifiers...
2010-05-27 Bob WilsonFix some bad fall-throughs in a switch statement. ...
2010-05-27 Jim Grosbachadd ISD::STACKADDR to get the current stack pointer...
2010-05-26 Jakob Stoklund OlesenGive SubRegIndex names to all ARM subregisters. This...
2010-05-26 Jim GrosbachAdjust eh.sjlj.setjmp to properly have a chain and...
2010-05-26 Jakob Stoklund OlesenReplace the SubRegSet tablegen class with a less error...
2010-05-26 Shih-wei LiaoCoding style change (Adding 1 missing space.)
2010-05-26 Shih-wei LiaoAdding the missing implementation for ARM::SBFX and...
2010-05-26 Jim Grosbachfix off by 1 (insn) error in eh.sjlj.setjmp thumb code...
2010-05-26 Jakob Stoklund OlesenRevert "Replace the SubRegSet tablegen class with a...
2010-05-26 Jakob Stoklund OlesenReplace the SubRegSet tablegen class with a less error...
2010-05-26 Shih-wei LiaoAdding the missing implementation of Bitfield's "clear...
2010-05-26 Shih-wei LiaoTo handle s* registers in emitVFPLoadStoreMultipleInstr...
2010-05-25 Jakob Stoklund OlesenRemove NumberHack entirely.
2010-05-25 Zonr ChangAdd missing implementation to the materialization of...
2010-05-25 Zonr ChangAdd support to MOVimm32 using movt/movw for ARM JIT
2010-05-25 Bob WilsonAllow t2MOVsrl_flag and t2MOVsra_flag instructions...
2010-05-25 Bob WilsonFix up instruction classes for Thumb2 RSB instructions...
2010-05-25 Bob WilsonClean up indentation.
2010-05-25 Jakob Stoklund OlesenUse enums instead of literals in the ARM backend.
2010-05-24 Jakob Stoklund OlesenSwitch SubRegSet to using symbolic SubRegIndices
2010-05-24 Bob WilsonAllow Thumb2 MVN instructions to set condition codes...
2010-05-24 Jakob Stoklund OlesenLose the dummies
2010-05-24 Jakob Stoklund OlesenReplace the tablegen RegisterClass field SubRegClassLis...
2010-05-24 Bob WilsonClean up some extra whitespace.
2010-05-24 Bob WilsonThumb2 RSBS instructions were being printed without...
2010-05-24 Evan ChengLR is in GPR, not tGPR even in Thumb1 mode.
2010-05-24 Jakob Stoklund OlesenFix a few places that depended on the numeric value...
2010-05-24 Jakob Stoklund OlesenSwitch ARMRegisterInfo.td to use SubRegIndex and elimin...
2010-05-23 Bob WilsonVDUP doesn't support vectors with 64-bit elements.
2010-05-22 Evan ChengImplement @llvm.returnaddress. rdar://8015977.
2010-05-22 Jim GrosbachImplement eh.sjlj.longjmp for ARM. Clean up the intrins...
2010-05-22 Bob WilsonRecognize more BUILD_VECTORs and VECTOR_SHUFFLEs that...
2010-05-21 Evan ChengChange ARM scheduling default to list-hybrid if the...
2010-05-20 Evan ChengAllow targets more controls on what nodes are scheduled...
2010-05-20 Bob WilsonHandle Neon v2f64 and v2i64 vector shuffles as register...
2010-05-19 Evan ChengCode refactoring: pull SchedPreference enum from Target...
2010-05-19 Evan Chengt2LEApcrel and tLEApcrel are re-materializable. This...
2010-05-19 Evan ChengUse 'adr' for LEApcrel and LEApcrel. Mark LEApcrel...
2010-05-19 Evan ChengMark pattern-less mayLoad / mayStore instructions never...
2010-05-19 Evan ChengTarget instruction selection should copy memoperands.
2010-05-19 Evan ChengMark a few more pattern-less instructions with neverHas...
2010-05-18 Evan ChengSink dag combine's post index load / store code that...
2010-05-17 Jakob Stoklund OlesenARMBaseRegisterInfo::estimateRSStackSizeLimit() could...
2010-05-17 Evan Chengvmov of immediates are trivially re-materializable.
2010-05-17 Bob WilsonFix a regression in 464.h264 for thumb1 and thumb2...
2010-05-17 Evan ChengTurn on -neon-reg-sequence by default.
2010-05-17 Evan ChengNo reason not to run the NEON domain croassing fix...
2010-05-16 Anton KorobeynikovChris said that the comment char should be escaped...
2010-05-16 Anton KorobeynikovGeneralize the ARM DAG combiner of mul with constants...
2010-05-16 Evan ChengModel vst lane instructions with REG_SEQUENCE.
2010-05-15 Anton KorobeynikovSome cheap DAG combine goodness for multiplication...
2010-05-15 Anton Korobeynikov"trap" pseudo-op turned out to be apple-local.
2010-05-15 Evan ChengModel 128-bit vld lane with REG_SEQUENCE.
2010-05-15 Evan Chengv4i64 and v8i64 are only synthesizable when NEON is...
2010-05-15 Evan ChengAllow TargetLowering::getRegClassFor() to be called...
2010-05-15 Evan ChengModel 64-bit lane vld with REG_SEQUENCE.
2010-05-14 Evan ChengTeach two-address pass to do some coalescing while...
2010-05-14 Evan ChengModel VST*_UPD and VST*oddUPD pair with REG_SEQUENCE.
2010-05-14 Bill WendlingRename "HasCalls" in MachineFrameInfo to "AdjustsStack...
2010-05-14 Evan ChengModel VLD*_UPD and VLD*odd_UPD pair with REG_SEQUENCE.
2010-05-14 Evan ChengAdded a QQQQ register file to model 4-consecutive Q...
2010-05-14 Evan ChengFix comments.
2010-05-13 Evan ChengAdd comment about the pseudo registers QQ, each of...
2010-05-13 Bob WilsonFix pr7110: For non-Darwin targets UnspilledCS1GPRs...
2010-05-13 Daniel DunbarFix -Asserts warning.
2010-05-13 Evan ChengBring back VLD1q and VST1q and use them for reloading...
2010-05-13 Evan ChengExpand VMOVQQ into a pair of VMOVQ.
2010-05-13 Evan ChengMark some pattern-less instructions as neverHasSideEffects.
2010-05-12 Evan ChengFix some potential issues in the pseudo instruction...
2010-05-12 Evan ChengRemove a dead fixme.
2010-05-12 Rafael EspindolaAdd support for movi32 of global values to the new...
2010-05-12 Evan Chengvst instructions are modeled as this:
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