Use SmallVectorImpl::iterator/const_iterator instead of SmallVector to avoid specifyi...
[oota-llvm.git] / lib / Target / ARM /
2013-07-04 Craig TopperUse SmallVectorImpl::iterator/const_iterator instead...
2013-07-04 Jakob Stoklund OlesenRevert r185595-185596 which broke buildbots.
2013-07-03 Jakob Stoklund OlesenRemove the EXCEPTIONADDR, EHSELECTION, and LSDAADDR...
2013-07-03 Stephen LinHave ARMBaseRegisterInfo::getCallPreservedMask return...
2013-07-03 Quentin Colombet[ARM] Improve the instruction selection of vector loads.
2013-07-03 Tilmann SchellerARM: Prevent ARMAsmParser::shouldOmitCCOutOperand(...
2013-07-03 Craig TopperUse SmallVectorImpl::iterator/const_iterator instead...
2013-07-03 Mihai PopaThis corrects the implementation of Thumb ADR instruct...
2013-07-03 Tim NorthoverARM: relax the atomic release barrier to "dmb ishst...
2013-07-02 Rafael EspindolaRemove address spaces from MC.
2013-07-02 Logan ChienFix ARM EHABI compact model 1 and 2 without handlerdata.
2013-07-01 Chad Rosier[ARMAsmParser] Sort the ARM register lists based on...
2013-07-01 Tim NorthoverRevert r185339 (ARM: relax the atomic release barrier...
2013-07-01 Tim NorthoverARM: relax the atomic release barrier to "dmb ishst"
2013-06-28 David BlaikieRemove unused member
2013-06-28 Eric ChristopherRemove unused variables.
2013-06-28 Weiming ZhaoBug 13662: Enable GPRPair for all i64 operands of inlin...
2013-06-28 Tim NorthoverARM: ensure fixed-point conversions have sane types
2013-06-28 Tilmann SchellerARM: Fix pseudo-instructions for SRS (Store Return...
2013-06-27 Joey GoulyAdd a Subtarget feature 'v8fp' to the ARM backend.
2013-06-26 Stephen LinClarify and doxygen-ify comments
2013-06-26 Stephen LinARM: Proactively ensure that the LowerCallResult hack...
2013-06-26 Stephen LinMinor formatting fix to ARMBaseRegisterInfo::getCalleeS...
2013-06-26 Joey GoulyAdd a subtarget feature 'v8' to the ARM backend.
2013-06-26 Tim NorthoverARM: fix more cases where predication may or may not...
2013-06-26 Tim NorthoverARM: allow predicated barriers in Thumb mode
2013-06-26 Joey GoulyRemove the 'generic' CPU from the ARM eabi attributes...
2013-06-26 Amaury de la VieuvilleARM: operands should be explicit when disassembled
2013-06-24 Amaury de la VieuvilleARM: check predicate bits for thumb instructions
2013-06-24 Amaury de la VieuvilleARM: rGPR is meant to be unpredictable, not undefined
2013-06-24 Amaury de la VieuvilleARM: fix thumb1 nop decoding
2013-06-24 Amaury de la VieuvilleARM: fix IT decoding
2013-06-24 Amaury de la VieuvilleARM: enable decoding of pc-relative PLD/PLI
2013-06-22 Chad RosierThe getRegForInlineAsmConstraint function should only...
2013-06-21 David BlaikieDebugInfo: Don't lose unreferenced non-trivial by-value...
2013-06-20 Quentin ColombetARM: Remove a (false) dependency on the memoryoperand...
2013-06-20 Joey GoulyThis reverts r155000.
2013-06-19 David BlaikieDebugInfo: PR14763/r183329 correct the location of...
2013-06-19 Bill WendlingAccess the TargetLoweringInfo from the TargetMachine...
2013-06-19 Bill WendlingAccess the TargetLoweringInfo from the TargetMachine...
2013-06-19 Bill WendlingAccess the TargetLoweringInfo from the TargetMachine...
2013-06-18 Jim GrosbachARM: Add optional datatype suffix to NEON mvn asm syntax.
2013-06-18 Michael Gottesman[ARMTargetLowering] ARMISD::{SUB,ADD}{C,E} second resul...
2013-06-18 Michael GottesmanConverted an overly aggressive assert to a conditional...
2013-06-18 Kevin EnderbyChange the arm assembler to support this from the v7c...
2013-06-18 David BlaikieReduce indentation.
2013-06-18 Amaury de la VieuvilleARM: fix literal load with positive offset encoding
2013-06-18 Amaury de la VieuvilleARM: add operands pre-writeback variants when needed
2013-06-18 Amaury de la VieuvilleARM: fix thumb literal loads decoding
2013-06-18 Amaury de la VieuvilleARM: thumb stores cannot use PC as dest register
2013-06-18 Bill WendlingUse pointers to the MCAsmInfo and MCRegInfo.
2013-06-16 David BlaikieDebugInfo: remove target-specific Frame Index handling...
2013-06-16 David BlaikieDebug Info: Simplify Frame Index handling in DBG_VALUE...
2013-06-15 Andrew TrickUpdate machine models. Specify buffer sizes for OOO...
2013-06-15 Andrew TrickMachine Model: Add MicroOpBufferSize and resource Buffe...
2013-06-14 Amaury de la VieuvilleARM: fix thumb coprocessor instruction with pre-writeba...
2013-06-14 JF BastienEnable FastISel on ARM for Linux and NaCl, not MCJIT
2013-06-13 Amaury de la VieuvilleARM: fix B decoding
2013-06-13 Amaury de la VieuvilleARM: fix t2am_imm8_offset operand printing for imm=#-0
2013-06-11 JF BastienARM FastISel fix sext/zext fold
2013-06-11 NAKAMURA TakumiRework r183728, suppress assert(0) for now. Its behavio...
2013-06-11 Mihai PopaIt adds support for negative zero offsets for loads...
2013-06-11 Mihai PopaThis patch adds support for FPINST/FPINST2 as operands...
2013-06-11 Amaury de la VieuvilleARM: Enforce decoding rules for VLDn instructions
2013-06-11 Amaury de la VieuvilleARM: Fix STREX/LDREX reecoding
2013-06-11 NAKAMURA TakumiTweak a couple of tests on win32 hosts with +Asserts.
2013-06-11 NAKAMURA TakumiARMAsmBackend.cpp: Use Triple::isOSBinFormatCOFF()...
2013-06-11 NAKAMURA TakumiWhitespace.
2013-06-10 Tim NorthoverARM: diagnose ARM/Thumb assembly switches on CPUs only...
2013-06-10 Aaron BallmanSilencing an MSVC warning about comparing signed and...
2013-06-10 Amaury de la VieuvilleFix misleading comments in ARMAsmParser
2013-06-10 Amaury de la VieuvilleARM: ISB cannot be passed the same options as DMB
2013-06-09 Logan ChienFix ARM unwind opcode assembler in several cases.
2013-06-09 JF BastienARM FastISel fix load register classes
2013-06-08 Amaury de la VieuvilleARM: fix VMOVvnf32 decoding when ambiguous with VCVT
2013-06-08 Amaury de la VieuvilleARM: enforce SRS decoding constraints
2013-06-08 Amaury de la VieuvilleARM: fix CPS decoding when ambiguous with QADD
2013-06-08 Amaury de la VieuvilleARM: fix VCVT decoding
2013-06-08 JF BastienFix unused variable warning from my previous patch.
2013-06-07 JF BastienARM FastISel integer sext/zext improvements
2013-06-07 Bill WendlingDon't cache the instruction and register info from...
2013-06-07 Arnold SchwaighoferARM sched model: Use the right resources for DIV
2013-06-07 Arnold SchwaighoferARM sched model: Add VFP div instruction on Swift
2013-06-07 Arnold SchwaighoferARM sched model: Add SIMD/VFP load/store instructions...
2013-06-06 Arnold SchwaighoferRevert "ARM sched model: Add SIMD/VFP load/store instru...
2013-06-06 Arnold SchwaighoferARM sched model: Add SIMD/VFP load/store instructions...
2013-06-06 Arnold SchwaighoferARM sched model: Add integer VFP/SIMD instructions...
2013-06-06 Arnold SchwaighoferARM sched model: Add integer load/store instructions...
2013-06-06 Arnold SchwaighoferARM sched model: Add integer arithmetic instructions...
2013-06-06 Arnold SchwaighoferARM sched model: Cortex A9 - More InstRW sched resources
2013-06-06 Arnold SchwaighoferARM sched model: Add branch thumb instructions
2013-06-06 Arnold SchwaighoferARM sched model: Add branch thumb2 instructions
2013-06-06 Arnold SchwaighoferARM sched model: Add branch instructions
2013-06-06 Arnold SchwaighoferARM sched model: Add preload thumb2 instructions
2013-06-06 Arnold SchwaighoferARM sched model: Add preload instructions
2013-06-06 Arnold SchwaighoferARM sched model: Add more ALU and CMP thumb instructions
2013-06-06 Arnold SchwaighoferARM sched model: Add more ALU and CMP thumb2 instructions
2013-06-06 Bill WendlingCache the TargetLowering info object as a pointer.
2013-06-05 Arnold SchwaighoferARM sched model: Add more ALU and CMP instructions
2013-06-05 Arnold SchwaighoferARM sched model: Add divsion, loads, branches, vfp cvt
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