Remove dead classes.
[oota-llvm.git] / lib / Target / ARM /
2011-08-15 Owen AndersonRemove dead classes.
2011-08-15 Owen AndersonFix incorrect encoding of UMAAL and friends. Patch...
2011-08-15 Owen AndersonFix decoding LDRSB and LDRSH in Thumb1 mode. Patch...
2011-08-15 Owen AndersonFix problems decoding the to/from-lane NEON memory...
2011-08-15 Jim GrosbachUpdate comment to reflect MC target machine refactor.
2011-08-13 Bob WilsonExpand VMOVQQQQ pseudo instructions.
2011-08-12 Jim GrosbachARM STR_POST_IMM offset encoding fix in load/store...
2011-08-12 Jim GrosbachARM expansion of pre-indexed store pseudos should maint...
2011-08-12 Owen AndersonFix some remaining issues with decoding ARM-mode memory...
2011-08-12 Owen AndersonFix decoding of ARM-mode STRH.
2011-08-12 Owen AndersonSpecify fixed bit in the LDRBT encoding, which allows...
2011-08-12 Owen AndersonFix decoding of pre-indexed stores.
2011-08-12 Owen AndersonSeparate decoding for STREXD and LDREXD to make each...
2011-08-12 Duncan SandsSilence a bunch (but not all) "variable written but...
2011-08-11 Jim GrosbachARM vector compare to zero instruction assembly parsing...
2011-08-11 Jim GrosbachRemove no-longer-true comments. These are for the assem...
2011-08-11 Jim GrosbachARM STRT assembly parsing and encoding.
2011-08-11 Owen AndersonMake the USAT16 operand decoder auto-generate-able.
2011-08-11 Owen AndersonAdd another accidentally omitted predicate operand.
2011-08-11 Owen AndersonAdd missing predicate operand on SMLA and friends.
2011-08-11 Jim GrosbachARM load shifted register pre-index fix shift value...
2011-08-11 Owen AndersonHandle new register classes in Thumb2 mode. Should...
2011-08-11 Owen AndersonMaking SEL decodings auto-generate-able.
2011-08-11 Jim GrosbachTidy up comment.
2011-08-11 Owen AndersonFix decoding support for STREXD and LDREXD.
2011-08-11 Jim GrosbachARM STRH assembly parsing and encoding.
2011-08-11 Owen AndersonFix decoding for indexed STRB and LDRB. Fixes <rdar...
2011-08-11 Jim GrosbachTidy up. Remove unused template parameter.
2011-08-11 Owen AndersonImprove operand validation for Thumb2 addressing modes.
2011-08-11 Jim GrosbachARM STRD assembly parsing and encoding.
2011-08-11 Owen AndersonContinue to tighten decoding by performing more operand...
2011-08-11 Jim GrosbachTidy up.
2011-08-11 Jim GrosbachARM STRBT assembly parsing and encoding.
2011-08-11 Jim GrosbachARM STR(immediate) assembly parsing and encoding.
2011-08-11 Owen AndersonTighten decoding of addrmode2 instructions to reject...
2011-08-11 Owen AndersonTighten operand decoding of addrmode2 instruction....
2011-08-11 Owen AndersonCorrect immediate range for shifter operands. Patch...
2011-08-11 Owen AndersonImprove error checking in the new ARM disassembler...
2011-08-11 Jim GrosbachARM push of a single register encodes as pre-indexed...
2011-08-11 Jim GrosbachARM pop of a single register encodes as post-indexed...
2011-08-10 Jim GrosbachARM LDRT assembly parsing and encoding.
2011-08-10 Jim GrosbachTidy up. 80 columns.
2011-08-10 Jim GrosbachARM LDRH(immediate) assembly parsing and encoding support.
2011-08-10 Jim GrosbachARM LDRD(register) assembly parsing and encoding.
2011-08-10 Jim GrosbachFix typo. Not quite sure how that slipped in there.
2011-08-10 Jim GrosbachARM LDRD(immediate) assembly parsing and encoding support.
2011-08-10 Owen AndersonAdd initial support for decoding NEON instructions...
2011-08-10 Owen AndersonTabs --> spaces.
2011-08-10 Owen AndersonCleanups based on Nick Lewycky's feedback.
2011-08-10 Owen AndersonRewrite some ARM InstrInfo functions to be most accepti...
2011-08-10 Rafael EspindolaAdd support for the R and Q constraints.
2011-08-10 Owen AndersonPush GPRnopc through a large number of instruction...
2011-08-09 Jakob Stoklund OlesenPromote VMOVS to VMOVD when possible.
2011-08-09 Owen AndersonTighten operand checking of register-shifted-register...
2011-08-09 Owen AndersonTighten operand checking on memory barrier instructions.
2011-08-09 Owen AndersonTighten operand checking on CPS instructions.
2011-08-09 Owen AndersonCreate a new register class for the set of all GPRs...
2011-08-09 Benjamin KramerARM Disassembler: sign extend branch immediates.
2011-08-09 Owen AndersonSilence an false-positive warning.
2011-08-09 Owen AndersonDon't generate the old-style disassembler in CMake...
2011-08-09 Benjamin KramerThe new ARM disassembler disassembles "bx lr" as a...
2011-08-09 Owen AndersonDon't continue generating the old-style decoder file.
2011-08-09 Jim GrosbachARM fix typo in pre-indexed store lowering.
2011-08-09 Owen AndersonAttempt to fix CMake build.
2011-08-09 Owen AndersonTighten Thumb1 branch predicate decoding.
2011-08-09 Owen AndersonReplace the existing ARM disassembler with a new one...
2011-08-09 Renato GolinEmitting ARM build attributes and values as ULEB, rathe...
2011-08-08 Jim GrosbachARM parsing and encoding for LDRBT instruction.
2011-08-08 Owen AndersonThumb1 BL instructions encoding 22 bits of displacement...
2011-08-08 Jakob Stoklund OlesenImplement isLoadFromStackSlotPostFE and isStoreToStackS...
2011-08-08 Jim GrosbachARM load/store label parsing.
2011-08-08 Owen AndersonFix encodings for Thumb ASR and LSR immediate operands...
2011-08-08 Eli FriedmanFix up the patterns for SXTB, SXTH, UXTB, and UXTH...
2011-08-08 Benjamin KramerAdd MCInstrAnalysis class. This allows the targets...
2011-08-05 Jim GrosbachARM load instruction shifted register index operands.
2011-08-05 Jim GrosbachARM indexed load assembly parsing and encoding.
2011-08-05 Jim GrosbachARM refactor indexed store instructions.
2011-08-05 Jim GrosbachARM simplify the postidx_reg operand encoding.
2011-08-05 Jim GrosbachARM use a dedicated printer for postidx_reg operands.
2011-08-05 Bob WilsonAdd missing register constraint for some VLD3/VLD4...
2011-08-04 Owen AndersonFix broken encodings for the Thumb2 LDRD/STRD instructions.
2011-08-04 Jim GrosbachARM assembly parsing and encoding for LDR instructions.
2011-08-04 Owen AndersonLDCL_POST and STCL_POST need one's-complement offsets...
2011-08-03 Jim GrosbachARM refactoring assembly parsing of memory address...
2011-08-03 Owen AndersonFix broken encoding of tCBNZ.
2011-08-03 Eli FriedmanNew approach to r136737: insert the necessary fences...
2011-08-02 Eli FriedmanARM backend support for atomicrmw and cmpxchg with...
2011-08-02 Owen AndersonFix the broken encodings for the VFP vmov.f32 and vmov...
2011-08-02 Jim GrosbachTidy up. 80 columns.
2011-08-02 Jim GrosbachARM: rename addrmode7 to addr_offset_none.
2011-08-01 Jim GrosbachMove imm0_255 to ARMInstrInfo.td with the other immedia...
2011-08-01 Jim GrosbachFix comments.
2011-08-01 Douglas GregorUpdate CMake target names for tablegen-generated data...
2011-07-29 Eric ChristopherAdd support for the 'Q' constraint.
2011-07-29 Jim GrosbachARM SRS instruction parsing, diassembly and encoding...
2011-07-29 Jim GrosbachARM CPS mode immediate is 5 bits, not 4.
2011-07-29 Jim GrosbachARM assembly parsing and encoding for RFE instruction.
2011-07-29 Jim GrosbachARM SRS and RFE instructions are not code-gen only.
2011-07-29 Jim GrosbachARM range checking for mode on CPS instruction.
2011-07-29 Jim GrosbachUpdate FIXME.
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