add ISD::STACKADDR to get the current stack pointer. Will be used by sjlj EH
[oota-llvm.git] / lib / Target / ARM /
2010-05-27 Jim Grosbachadd ISD::STACKADDR to get the current stack pointer...
2010-05-26 Jakob Stoklund OlesenGive SubRegIndex names to all ARM subregisters. This...
2010-05-26 Jim GrosbachAdjust eh.sjlj.setjmp to properly have a chain and...
2010-05-26 Jakob Stoklund OlesenReplace the SubRegSet tablegen class with a less error...
2010-05-26 Shih-wei LiaoCoding style change (Adding 1 missing space.)
2010-05-26 Shih-wei LiaoAdding the missing implementation for ARM::SBFX and...
2010-05-26 Jim Grosbachfix off by 1 (insn) error in eh.sjlj.setjmp thumb code...
2010-05-26 Jakob Stoklund OlesenRevert "Replace the SubRegSet tablegen class with a...
2010-05-26 Jakob Stoklund OlesenReplace the SubRegSet tablegen class with a less error...
2010-05-26 Shih-wei LiaoAdding the missing implementation of Bitfield's "clear...
2010-05-26 Shih-wei LiaoTo handle s* registers in emitVFPLoadStoreMultipleInstr...
2010-05-25 Jakob Stoklund OlesenRemove NumberHack entirely.
2010-05-25 Zonr ChangAdd missing implementation to the materialization of...
2010-05-25 Zonr ChangAdd support to MOVimm32 using movt/movw for ARM JIT
2010-05-25 Bob WilsonAllow t2MOVsrl_flag and t2MOVsra_flag instructions...
2010-05-25 Bob WilsonFix up instruction classes for Thumb2 RSB instructions...
2010-05-25 Bob WilsonClean up indentation.
2010-05-25 Jakob Stoklund OlesenUse enums instead of literals in the ARM backend.
2010-05-24 Jakob Stoklund OlesenSwitch SubRegSet to using symbolic SubRegIndices
2010-05-24 Bob WilsonAllow Thumb2 MVN instructions to set condition codes...
2010-05-24 Jakob Stoklund OlesenLose the dummies
2010-05-24 Jakob Stoklund OlesenReplace the tablegen RegisterClass field SubRegClassLis...
2010-05-24 Bob WilsonClean up some extra whitespace.
2010-05-24 Bob WilsonThumb2 RSBS instructions were being printed without...
2010-05-24 Evan ChengLR is in GPR, not tGPR even in Thumb1 mode.
2010-05-24 Jakob Stoklund OlesenFix a few places that depended on the numeric value...
2010-05-24 Jakob Stoklund OlesenSwitch ARMRegisterInfo.td to use SubRegIndex and elimin...
2010-05-23 Bob WilsonVDUP doesn't support vectors with 64-bit elements.
2010-05-22 Evan ChengImplement @llvm.returnaddress. rdar://8015977.
2010-05-22 Jim GrosbachImplement eh.sjlj.longjmp for ARM. Clean up the intrins...
2010-05-22 Bob WilsonRecognize more BUILD_VECTORs and VECTOR_SHUFFLEs that...
2010-05-21 Evan ChengChange ARM scheduling default to list-hybrid if the...
2010-05-20 Evan ChengAllow targets more controls on what nodes are scheduled...
2010-05-20 Bob WilsonHandle Neon v2f64 and v2i64 vector shuffles as register...
2010-05-19 Evan ChengCode refactoring: pull SchedPreference enum from Target...
2010-05-19 Evan Chengt2LEApcrel and tLEApcrel are re-materializable. This...
2010-05-19 Evan ChengUse 'adr' for LEApcrel and LEApcrel. Mark LEApcrel...
2010-05-19 Evan ChengMark pattern-less mayLoad / mayStore instructions never...
2010-05-19 Evan ChengTarget instruction selection should copy memoperands.
2010-05-19 Evan ChengMark a few more pattern-less instructions with neverHas...
2010-05-18 Evan ChengSink dag combine's post index load / store code that...
2010-05-17 Jakob Stoklund OlesenARMBaseRegisterInfo::estimateRSStackSizeLimit() could...
2010-05-17 Evan Chengvmov of immediates are trivially re-materializable.
2010-05-17 Bob WilsonFix a regression in 464.h264 for thumb1 and thumb2...
2010-05-17 Evan ChengTurn on -neon-reg-sequence by default.
2010-05-17 Evan ChengNo reason not to run the NEON domain croassing fix...
2010-05-16 Anton KorobeynikovChris said that the comment char should be escaped...
2010-05-16 Anton KorobeynikovGeneralize the ARM DAG combiner of mul with constants...
2010-05-16 Evan ChengModel vst lane instructions with REG_SEQUENCE.
2010-05-15 Anton KorobeynikovSome cheap DAG combine goodness for multiplication...
2010-05-15 Anton Korobeynikov"trap" pseudo-op turned out to be apple-local.
2010-05-15 Evan ChengModel 128-bit vld lane with REG_SEQUENCE.
2010-05-15 Evan Chengv4i64 and v8i64 are only synthesizable when NEON is...
2010-05-15 Evan ChengAllow TargetLowering::getRegClassFor() to be called...
2010-05-15 Evan ChengModel 64-bit lane vld with REG_SEQUENCE.
2010-05-14 Evan ChengTeach two-address pass to do some coalescing while...
2010-05-14 Evan ChengModel VST*_UPD and VST*oddUPD pair with REG_SEQUENCE.
2010-05-14 Bill WendlingRename "HasCalls" in MachineFrameInfo to "AdjustsStack...
2010-05-14 Evan ChengModel VLD*_UPD and VLD*odd_UPD pair with REG_SEQUENCE.
2010-05-14 Evan ChengAdded a QQQQ register file to model 4-consecutive Q...
2010-05-14 Evan ChengFix comments.
2010-05-13 Evan ChengAdd comment about the pseudo registers QQ, each of...
2010-05-13 Bob WilsonFix pr7110: For non-Darwin targets UnspilledCS1GPRs...
2010-05-13 Daniel DunbarFix -Asserts warning.
2010-05-13 Evan ChengBring back VLD1q and VST1q and use them for reloading...
2010-05-13 Evan ChengExpand VMOVQQ into a pair of VMOVQ.
2010-05-13 Evan ChengMark some pattern-less instructions as neverHasSideEffects.
2010-05-12 Evan ChengFix some potential issues in the pseudo instruction...
2010-05-12 Evan ChengRemove a dead fixme.
2010-05-12 Rafael EspindolaAdd support for movi32 of global values to the new...
2010-05-12 Evan Chengvst instructions are modeled as this:
2010-05-11 Evan ChengAvoid breaking vstd when reg_sequence is not used.
2010-05-11 Duncan SandsI got tired of VISIBILITY_HIDDEN colliding with the...
2010-05-11 Dan GohmanImplement a bunch more TargetSelectionDAGInfo infrastru...
2010-05-11 Dan GohmanRemove the TargetLowering::getSubtarget() virtual funct...
2010-05-11 Evan ChengSelect @llvm.trap to the special B with 1111 condition...
2010-05-11 Evan ChengModel some vst3 and vst4 with reg_sequence.
2010-05-10 Evan ChengModel some vld3 instructions with REG_SEQUENCE.
2010-05-10 Evan ChengModel vld2 / vst2 with reg_sequence.
2010-05-07 Jim GrosbachClean up the conditional for handling of sign_extend_in...
2010-05-07 Evan ChengUse VLD2q32 / VST2q32 to reload / spill QQ (pair of...
2010-05-07 Evan ChengUse VSTMD / VLDMD for spills and reloads of Q registers...
2010-05-07 Evan ChengRemove VLD1q and VST1q for reloading and spilling Q...
2010-05-06 Dan GohmanAdd a DebugLoc argument to TargetInstrInfo::copyRegToRe...
2010-05-06 Evan ChengAdd argument TargetRegisterInfo to loadRegFromStackSlot...
2010-05-06 Bob WilsonAdd a missing break statement to fix unintentional...
2010-05-06 Jim GrosbachFix unintentional fallthrough. Patch by Edmund Grimley...
2010-05-06 Shantonu SenFix "warning: extra ';' inside a struct or union" when...
2010-05-06 Evan ChengRe-apply 103156 and 103157. 103156 didn't break anythin...
2010-05-06 Dan GohmanRevert r103157, which broke test/CodeGen/ARM/2009-11...
2010-05-06 Eric ChristopherRevert r103156 since it was breaking the build bots.
2010-05-06 Evan ChengFix an obvious bug in isMoveInstr. It needs to return...
2010-05-06 Evan ChengAdding pseudo 256-bit registers QQ0 . . . QQ7 to repres...
2010-05-06 Evan ChengCosmetic changes.
2010-05-06 Evan ChengstoreRegToStackSlot has forgotten about QPR_8 register...
2010-05-05 Jim GrosbachCleanup of ARMv7M support. Move hardware divide and...
2010-05-05 Evan ChengDo not pre-allocate references of D registers pairs...
2010-05-05 Jim GrosbachAdd initial support for ARMv7M subtarget and cortex...
2010-05-05 Evan ChengModel CONCAT_VECTORS of two 64-bit values as a REG_SEQU...
2010-05-04 Evan ChengWith -neon-reg-sequence, models forming a Q register...
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