2014-12-19 |
Colin LeMahieu | [Hexagon] Removing old variants of instructions and... |
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2014-12-19 |
Colin LeMahieu | [Hexagon] Adding bit extraction and table indexing... |
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2014-12-19 |
Colin LeMahieu | [Hexagon] Adding bit insertion instructions. |
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2014-12-19 |
Colin LeMahieu | [Hexagon] Adding more xtype shift instructions. |
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2014-12-19 |
Colin LeMahieu | [Hexagon] Adding xtype shift instructions. |
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2014-12-19 |
Colin LeMahieu | [Hexagon] Adding transfers to and from control registers. |
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2014-12-19 |
Colin LeMahieu | [Hexagon] Adding doubleregs for control registers.... |
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2014-12-19 |
Colin LeMahieu | [Hexagon] Adding loop0/1 sp0/1/2loop0 instructions. |
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2014-12-18 |
Colin LeMahieu | Reverting 224550, was not ready for commit. |
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2014-12-18 |
Colin LeMahieu | [Hexagon] Adding loop0/1 sp0/1/2loop0 instructions. |
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2014-12-16 |
Colin LeMahieu | [Hexagon] Updating doubleword shift usages to new versions. |
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2014-12-16 |
Colin LeMahieu | [Hexagon] Removing old XTYPE/BIT instructions and repla... |
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2014-12-16 |
Colin LeMahieu | [Hexagon] Adding tstbit/bitclr/bitset instructions. |
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2014-12-16 |
Colin LeMahieu | [Hexagon] Adding bit count and twiddling instructions. |
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2014-12-16 |
Colin LeMahieu | [Hexagon] Adding asr/lsr/asl reg/imm, asl with saturati... |
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2014-12-16 |
Colin LeMahieu | [Hexagon] Adding absolute value, and negate with saturation |
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2014-12-16 |
Colin LeMahieu | [Hexagon] Adding saturate and swizzle instructions. |
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2014-12-16 |
Colin LeMahieu | [Hexagon] Removing old multiply defs and updating refer... |
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2014-12-16 |
Colin LeMahieu | [Hexagon] Adding doubleword multiplies with and without... |
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2014-12-15 |
Colin LeMahieu | [Hexagon] Adding halfword to doubleword multiplies. |
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2014-12-15 |
Colin LeMahieu | [Hexagon] Adding logical-logical accumulation instructi... |
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2014-12-15 |
Colin LeMahieu | [Hexagon] Adding a number of additional multiply forms... |
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2014-12-15 |
Colin LeMahieu | [Hexagon] Adding misc multiply encodings and tests. |
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2014-12-15 |
Colin LeMahieu | [Hexagon] Adding doubleworld accumulating multiplies... |
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2014-12-15 |
Colin LeMahieu | [Hexagon] Adding accumulating half word multiplies. |
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2014-12-15 |
Colin LeMahieu | [Hexagon] Adding multiply with rnd/sat/rndsat |
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2014-12-15 |
Colin LeMahieu | [Hexagon] Adding encoding bits for halfword multiplies. |
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2014-12-11 |
Colin LeMahieu | [Hexagon] Renaming classes in preparation for replacement. |
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2014-12-11 |
Colin LeMahieu | [Hexagon] Ading i64 <- i32, i32 sextw pattern. |
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2014-12-11 |
Colin LeMahieu | [Hexagon] Adding encoding information for sign extend... |
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2014-12-10 |
Colin LeMahieu | [Hexagon] Adding encodings for JR class instructions... |
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2014-12-10 |
Colin LeMahieu | [Hexagon] Adding JR class predicated call reg instructions. |
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2014-12-09 |
Colin LeMahieu | [Hexagon] [NFC] Cleaning up unused classes. |
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2014-12-09 |
Colin LeMahieu | [Hexagon] Fixing broken tests. |
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2014-12-09 |
Colin LeMahieu | [Hexagon] Updating rr/ri 32/64 transfer encodings and... |
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2014-12-09 |
Colin LeMahieu | [Hexagon] Adding word combine dot-new form and replacin... |
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2014-12-09 |
Colin LeMahieu | [Hexagon] Updating predicate register transfers and... |
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2014-12-08 |
Colin LeMahieu | [Hexagon] Removing old def versions and replacing usage... |
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2014-12-08 |
Colin LeMahieu | [Hexagon] Adding any8, all8, and/or/xor/andn/orn/not... |
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2014-12-08 |
Colin LeMahieu | [Hexagon] Adding xtype doubleword add, sub, and, or... |
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2014-12-08 |
Colin LeMahieu | [Hexagon] Adding xtype doubleword comparisons. Removin... |
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2014-12-08 |
Colin LeMahieu | [Hexagon] Adding xtype parity, min, minu, max, maxu... |
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2014-12-08 |
Colin LeMahieu | [Hexagon] Adding xtype halfword add/sub ll/hl/lh/hh... |
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2014-12-08 |
Colin LeMahieu | [Hexagon] Adding add/sub with saturation. Removing... |
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2014-12-08 |
Colin LeMahieu | [Hexagon] Adding combine reg, reg with predicated forms. |
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2014-12-08 |
Colin LeMahieu | [Hexagon] Adding packhl instruction. |
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2014-12-05 |
Colin LeMahieu | [Hexagon] Relocating logical instructions and templates... |
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2014-12-05 |
Colin LeMahieu | [Hexagon] Adding sub/and/or reg, imm forms |
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2014-12-05 |
Colin LeMahieu | [Hexagon] Updating mux_ir/ri/ii/rr with encoding bits |
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2014-12-05 |
Colin LeMahieu | [Hexagon] Adding tfrih/l instructions. |
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2014-12-05 |
Colin LeMahieu | [Hexagon] Adding add reg, imm form with encoding bits... |
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2014-12-05 |
Colin LeMahieu | [Hexagon] Adding DoubleRegs decoder. Moving C2_mux... |
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2014-12-05 |
Colin LeMahieu | [Hexagon] [NFC] Rearranging patterns and mux instruction. |
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2014-12-05 |
Colin LeMahieu | [Hexagon] [NFC] Rearranging def order. |
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2014-12-05 |
Colin LeMahieu | [Hexagon] Adding combine reg-reg forms. |
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2014-12-05 |
Colin LeMahieu | [Hexagon] Marking several instructions as isCodeGenOnly... |
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2014-12-04 |
Colin LeMahieu | [Hexagon] Marking some instructions as CodeGenOnly... |
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2014-11-26 |
Colin LeMahieu | [Hexagon] Adding cmp* immediate form instructions. |
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2014-11-26 |
Colin LeMahieu | [Hexagon] Adding and64, or64, and xor64 instructions. |
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2014-11-26 |
Craig Topper | Replace neverHasSideEffects=1 with hasSideEffects=0... |
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2014-11-25 |
Colin LeMahieu | [Hexagon] Adding add64 and sub64 instructions. |
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2014-11-25 |
Colin LeMahieu | Reverting 222792 |
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2014-11-25 |
Colin LeMahieu | [Hexagon] Adding compare with immediate instructions. |
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2014-11-25 |
Colin LeMahieu | [Hexagon] Adding NOP encoding bits. |
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2014-11-25 |
Colin LeMahieu | [Hexagon] Adding C2_mux instruction. |
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2014-11-25 |
Colin LeMahieu | [Hexagon] Replacing cmp* instructions with ones that... |
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2014-11-24 |
Colin LeMahieu | [Hexagon] Adding asrh instruction, removing unused... |
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2014-11-24 |
Colin LeMahieu | [Hexagon] Adding aslh instruction. |
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2014-11-24 |
Colin LeMahieu | [Hexagon] Adding zxth instruction. |
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2014-11-24 |
Colin LeMahieu | [Hexagon] Adding zxtb instruction. |
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2014-11-21 |
Colin LeMahieu | [Hexagon] Adding sxth instruction. |
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2014-11-21 |
Colin LeMahieu | [Hexagon] Adding sxtb instruction. Renaming some ident... |
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2014-11-21 |
Colin LeMahieu | [Hexagon] Removing SUB_rr and replacing with A2_sub. |
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2014-11-19 |
Colin LeMahieu | [Hexagon] Adding A2_xor instruction with IR selection... |
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2014-11-19 |
Colin LeMahieu | [Hexagon] Adding A2_or instruction with IR selection... |
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2014-11-18 |
Colin LeMahieu | [Hexagon] Adding A2_and instruction. |
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2014-11-18 |
Colin LeMahieu | [Hexagon] Adding A2_sub instruction |
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2014-11-18 |
Colin LeMahieu | [Hexagon] Converting from ADD_rr to A2_add which has... |
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2014-11-04 |
Colin LeMahieu | [Hexagon] Reverting 220584 to address ASAN errors. |
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2014-10-24 |
Colin LeMahieu | [Hexagon] Resubmission of 220427 |
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2014-10-23 |
NAKAMURA Takumi | Revert r220427, "[Hexagon] Adding encoding bits for... |
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2014-10-22 |
Colin LeMahieu | [Hexagon] Adding encoding bits for add opcode. |
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2014-10-22 |
Colin LeMahieu | [Hexagon] Adding basic disassembler. |
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2014-05-07 |
Jyotsna Verma | [Hexagon] Add New TSFlags to be used in the upcoming... |
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2013-05-14 |
Jyotsna Verma | Hexagon: Pass to replace tranfer/copy instructions... |
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2013-05-07 |
Jyotsna Verma | Hexagon: Set accessSize and addrMode on all load/store... |
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2013-05-02 |
Pranav Bhandarkar | Hexagon - Add peephole optimizations for zero extends. |
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2013-05-01 |
Jyotsna Verma | Hexagon: Use multiclass for Jump instructions. |
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2013-04-23 |
Jyotsna Verma | Hexagon: Use multiclass for combine and STri[bhwd]_shl_... |
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2013-04-23 |
Jyotsna Verma | Hexagon: Remove assembler mapped instruction definitions. |
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2013-04-12 |
Jyotsna Verma | Hexagon: Set isPredicatedNew flag on predicate new... |
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2013-04-12 |
Jyotsna Verma | Hexagon: Set isPredicatedFlase flag for all the instruc... |
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2013-03-28 |
Jyotsna Verma | Hexagon: Replace switch-case in isDotNewInst with TSFlags. |
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2013-03-28 |
Jyotsna Verma | Hexagon: Use multiclass for gp-relative instructions. |
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2013-03-26 |
Jyotsna Verma | Hexagon: Use multiclass for aslh, asrh, sxtb, sxth... |
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2013-03-08 |
Jyotsna Verma | Hexagon: Add patterns for zero extended loads from... |
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2013-03-07 |
Jyotsna Verma | Hexagon: Add support to lower block address. |
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2013-03-05 |
Jyotsna Verma | reverting patch 176508. |
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2013-03-05 |
Jyotsna Verma | Hexagon: Add support for lowering block address. |
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2013-03-05 |
Jyotsna Verma | Hexagon: Add encoding bits to the TFR64 instructions. |
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