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ARM two-operand aliases for VRHADD instructions.
[oota-llvm.git]
/
lib
/
Target
/
Hexagon
/
HexagonRegisterInfo.cpp
2012-04-16
Sirish Pande
Hexagon V5 (Floating Point) Support.
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2012-03-17
Craig Topper
Reorder includes in Target backends to following coding...
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2012-03-04
Craig Topper
Use uint16_t to store registers in callee saved registe...
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2012-02-22
Sirish Pande
Efficient pattern for store truncate. Patch by Evandro...
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2012-02-18
Jia Liu
Emacs-tag and some comment fix for all ARM, CellSPU...
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2012-02-07
Craig Topper
Convert assert(0) to llvm_unreachable
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2012-02-06
Benjamin Kramer
Hexagon: Remove forbidden iostream includes (it introdu...
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2011-12-27
Benjamin Kramer
Clean up some Release build warnings.
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2011-12-15
Tony Linthicum
Add MCTargetDesc library to Hexagon target
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2011-12-12
Tony Linthicum
Hexagon backend support
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