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ARM Scheduler Model: Partial implementation of the new machine scheduler model
[oota-llvm.git]
/
lib
/
Target
/
MSP430
/
MSP430RegisterInfo.td
2012-05-04
Jakob Stoklund Olesen
Remove the SubRegClasses field from RegisterClass descr...
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2012-02-18
Jia Liu
Emacs-tag and some comment fix for all ARM, CellSPU...
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2011-06-15
Jakob Stoklund Olesen
Use set operations instead of plain lists to enumerate...
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2011-06-09
Jakob Stoklund Olesen
Remove custom allocation order boilerplate that is...
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2011-01-10
Anton Korobeynikov
Rename TargetFrameInfo into TargetFrameLowering. Also...
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2010-11-18
Anton Korobeynikov
Move hasFP() and few related hooks to TargetFrameInfo.
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2010-05-26
Jakob Stoklund Olesen
Replace the SubRegSet tablegen class with a less error...
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2010-05-26
Jakob Stoklund Olesen
Revert "Replace the SubRegSet tablegen class with a...
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2010-05-26
Jakob Stoklund Olesen
Replace the SubRegSet tablegen class with a less error...
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2010-05-25
Jakob Stoklund Olesen
Remove NumberHack entirely.
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2010-05-24
Jakob Stoklund Olesen
Switch SubRegSet to using symbolic SubRegIndices
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2010-05-24
Jakob Stoklund Olesen
Replace the tablegen RegisterClass field SubRegClassLis...
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2010-05-24
Jakob Stoklund Olesen
SubRegIndex'ize MSP430
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2009-05-03
Anton Korobeynikov
Add normal and trunc stores
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2009-05-03
Anton Korobeynikov
Add 8-bit regclass and pattern for sext_inreg
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2009-05-03
Anton Korobeynikov
gas uses lower letter for register names
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2009-05-03
Anton Korobeynikov
Add code enough for emission of reg-reg and reg-imm...
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2009-05-03
Anton Korobeynikov
Fix register names, fix register allocation order,...
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2009-05-03
Anton Korobeynikov
Typo
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2009-05-03
Anton Korobeynikov
Dummy MSP430 backend
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