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R600/SI: Add VI versions of MUBUF atomics
[oota-llvm.git]
/
lib
/
Target
/
R600
/
AMDGPUISelLowering.cpp
2015-01-26
Eric Christopher
Move DataLayout back to the TargetMachine from TargetSu...
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2015-01-23
Tom Stellard
R600/SI: Move i64 -> v2i32 load promotion into AMDGPUDA...
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2015-01-22
Jan Vesely
R600: Try to use lower types for 64bit division if...
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2015-01-22
Jan Vesely
R600: Simplify LowerUDIVREM
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2015-01-21
Matt Arsenault
R600/SI: Custom lower fround
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2015-01-14
Matt Arsenault
Implement new way of expanding extloads.
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2015-01-13
Matt Arsenault
R600: Implement getRecipEstimate
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2015-01-13
Matt Arsenault
R600: Implement getRsqrtEstimate
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2015-01-13
Matt Arsenault
R600: Make cttz / ctlz cheap to speculate
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2015-01-08
Ahmed Bougacha
[SelectionDAG] Allow targets to specify legality of...
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2015-01-06
Matt Arsenault
R600/SI: Add class intrinsic
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2014-12-19
Matt Arsenault
R600: Remove outdated comment
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2014-12-19
Matt Arsenault
R600/SI: Only form min/max with 1 use.
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2014-12-12
Matt Arsenault
R600: Fix min/max matching problems with unordered...
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2014-12-12
Matt Arsenault
Add target hook for whether it is profitable to reduce...
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2014-12-07
Marek Olsak
R600/SI: Update instruction conversions for VI
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2014-11-26
Matt Arsenault
R600/SI: Use ZeroOrNegativeOneBooleanContent
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2014-11-23
Matt Arsenault
R600: Fix assert on copy of an i1 on pre-SI
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2014-11-15
Matt Arsenault
R600: Permute operands when selecting legacy min/max
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2014-11-15
Tom Stellard
R600: Fix 64-bit integer division
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2014-11-15
Tom Stellard
R600: Factor i64 UDIVREM lowering into its own fuction
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2014-11-14
Matt Arsenault
R600/SI: Combine min3/max3 instructions
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2014-11-14
Matt Arsenault
R600/SI: Match integer min / max instructions
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2014-11-13
Matt Arsenault
R600/SI: Fix fmin_legacy / fmax_legacy matching for SI
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2014-11-13
Aditya Nandakumar
We can get the TLOF from the TargetMachine - so constru...
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2014-11-13
Matt Arsenault
R600: Error on initializer for LDS.
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2014-11-13
Aditya Nandakumar
This patch changes the ownership of TLOF from TargetLow...
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2014-10-21
Matt Arsenault
Add minnum / maxnum codegen
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2014-10-21
Matt Arsenault
R600/SI: Add missing parameter to div_fmas intrinsic
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2014-10-16
Matt Arsenault
R600: Fix nonsensical implementation of computeKnownBit...
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2014-10-16
Matt Arsenault
R600: Remove dead function
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2014-10-15
Matt Arsenault
R600: Remove unnecessary part of computeKnownBitsForTar...
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2014-10-15
Matt Arsenault
Move variable down to use
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2014-10-15
Matt Arsenault
R600: Fix miscompiles when BFE has multiple uses
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2014-10-15
Matt Arsenault
R600: Use existing variable
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2014-10-15
Matt Arsenault
R600: Remove outdated comment
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2014-10-03
Matt Arsenault
R600/SI: Custom lower f64 -> i64 conversions
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2014-10-03
Matt Arsenault
R600: Custom lower [s|u]int_to_fp for i64 -> f64
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2014-10-03
Matt Arsenault
R600/SI: Fix ftrunc f64 conformance failures.
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2014-09-26
Matt Arsenault
R600/SI: Add a note about the order of the operands...
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2014-09-22
Tom Stellard
R600: Don't set BypassSlowDiv for 64-bit division
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2014-09-22
Tom Stellard
R600/SI: Use ISD::MUL instead of ISD::UMULO when loweri...
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2014-09-19
Matt Arsenault
R600: Better fix for bug 20982
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2014-09-18
Matt Arsenault
R600: Bug 20982 - Avoid undefined left shift of negativ...
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2014-09-10
Matt Arsenault
R600: Custom lower frem
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2014-08-29
Matt Arsenault
R600/SI: Use mad for fsub + fmul
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2014-08-21
Sanjay Patel
name change: isPow2DivCheap -> isPow2SDivCheap
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2014-08-15
Matt Arsenault
R600/SI: Use source modifiers for f64 fneg
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2014-08-15
Matt Arsenault
R600/SI: Use source modifier for f64 fabs
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2014-08-15
Matt Arsenault
R600/SI: Add intrinsic for ldexp
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2014-08-12
Jan Vesely
R600: Use optimized 24bit path in udivrem
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2014-08-12
Jan Vesely
R600: Remove unused code.
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2014-08-12
Jan Vesely
R600: Use i24 optimized path for SREM
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2014-08-09
Matt Arsenault
R600: Disable FP exceptions.
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2014-08-05
Tom Stellard
R600/SI: Avoid generating REGISTER_LOAD instructions.
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2014-08-04
Eric Christopher
Remove the TargetMachine forwards for TargetSubtargetIn...
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2014-08-04
Matt Arsenault
Use the known address space constant rather than checki...
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2014-08-01
Tom Stellard
Revert "R600: Move code for generating REGISTER_LOAD...
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2014-08-01
Tom Stellard
R600: Move code for generating REGISTER_LOAD into R600I...
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2014-07-31
Louis Gerbarg
Make sure no loads resulting from load->switch DAGCombi...
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2014-07-25
Chandler Carruth
[SDAG] Enable the new assert for out-of-range result...
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2014-07-24
Matt Arsenault
R600: Add new functions for splitting vector loads...
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2014-07-24
Matt Arsenault
R600: Fix LowerSDIV24
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2014-07-21
Tom Stellard
R600/SI: Store constant initializer data in constant...
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2014-07-18
Tim Northover
R600: support fpext/fptrunc operations to and from...
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2014-07-18
Tim Northover
R600: support f16 -> f64 conversion intrinsic.
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2014-07-15
Jan Vesely
R600: Implement zero undef variants of ctlz/cttz
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2014-07-15
Matt Arsenault
R600: Add dag combine for copy of an illegal type.
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2014-07-10
Jan Vesely
R600: Implement float to long/ulong
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2014-07-07
Matt Arsenault
R600: Fix mishandling of load / store chains.
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2014-07-02
Tom Stellard
R600: Add a comment that llvm.AMDGPU.trunc is a legacy...
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2014-07-02
Tom Stellard
R600: Promote i64 loads to v2i32
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2014-07-02
Matt Arsenault
R600: Fix crashes when an illegal type load or store...
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2014-06-30
Matt Arsenault
R600: Move mul combine to separate function
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2014-06-27
Matt Arsenault
R600: Move load/store ReplaceNodeResults to common...
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2014-06-26
Aaron Ballman
Silencing a warning about isZExtFree hiding an inherite...
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2014-06-26
Matt Arsenault
R600: Fix vector FMA
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2014-06-24
Tom Stellard
R600: Promote i64 stores to v2i32
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2014-06-24
Matt Arsenault
R600: Fix inconsistency in rsq instructions.
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2014-06-24
Matt Arsenault
R600: Remove DIV_INF
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2014-06-23
Matt Arsenault
R600/SI: Fix div_scale intrinsic.
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2014-06-23
Matt Arsenault
R600: Remove AMDILISelLowering
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2014-06-23
Matt Arsenault
R600: Select is not expensive.
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2014-06-23
Matt Arsenault
R600: Move add/sub with overflow out of AMDILISelLowering
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2014-06-23
Matt Arsenault
R600: Move more out of AMDILISelLowering
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2014-06-23
Matt Arsenault
R600/SI: Handle i64 sub.
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2014-06-23
Matt Arsenault
R600: Rename AMDIL file
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2014-06-22
Jan Vesely
R600: Use LowerSDIVREM for i64 node replace
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2014-06-22
Jan Vesely
R600: Implement custom SDIVREM.
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2014-06-20
Tom Stellard
R600/SI: Add a pattern for f32 ftrunc
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2014-06-20
Tom Stellard
R600: Expand vector flog2
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2014-06-20
Tom Stellard
R600: Expand vector fexp2
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2014-06-19
Matt Arsenault
R600/SI: Add intrinsics for various math instructions.
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2014-06-18
Matt Arsenault
Use stdint macros for specifying size of constants
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2014-06-18
Matt Arsenault
R600: Handle fnearbyint
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2014-06-18
Matt Arsenault
Use LL suffix for literal that should be 64-bits.
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2014-06-18
Jan Vesely
R600: Expand vector fceil
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2014-06-18
Matt Arsenault
Work around ridiculous warning.
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2014-06-18
Matt Arsenault
R600/SI: Add intrinsics for brev instructions
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2014-06-18
Matt Arsenault
R600: Implement f64 ftrunc, ffloor and fceil.
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