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In preparation for moving ARM's TargetRegisterInfo to the TargetMachine
[oota-llvm.git]
/
lib
/
Target
/
R600
/
R600ISelLowering.h
2015-01-30
Eric Christopher
Reuse a bunch of cached subtargets and remove getSubtar...
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2014-08-13
Benjamin Kramer
Canonicalize header guards into a common format.
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2014-06-23
Matt Arsenault
R600: Remove AMDILISelLowering
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2014-06-18
Jan Vesely
R600: Implement 64bit SRL
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2014-06-18
Jan Vesely
R600: Implement 64bit SHL
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2014-06-17
Tom Stellard
R600: Use LDS and vectors for private memory
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2014-06-13
Matt Arsenault
R600/SI: Fix selection error on i64 rotl / rotr.
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2014-04-29
Craig Topper
[C++11] Add 'override' keywords and remove 'virtual...
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2014-03-27
Matt Arsenault
R600/SI: Fix unreachable with a sext_in_reg to an illeg...
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2014-01-24
Alp Toker
Fix known typos
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2013-11-13
Tom Stellard
R600/SI: Add support for private address space load...
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2013-09-12
Vincent Lejeune
R600: Move fabs/fneg/sel folding logic into PostProcessIsel
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2013-09-05
Tom Stellard
R600: Expand SELECT nodes rather than custom lowering...
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2013-07-09
Vincent Lejeune
R600: Use DAG lowering pass to handle fcos/fsin
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2013-06-07
Bill Wendling
Don't cache the instruction and register info from...
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2013-06-04
Vincent Lejeune
R600: Swizzle texture/export instructions
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2013-05-25
Andrew Trick
Track IR ordering of SelectionDAG nodes 2/4.
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2013-05-18
Matt Arsenault
Add LLVMContext argument to getSetCCResultType
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2013-03-22
Michel Danzer
R600: Use legacy (0 * anything = 0) MUL instructions...
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2013-03-08
Tom Stellard
R600: Change operation action from Custom to Expand...
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2013-03-08
Tom Stellard
R600: Change operation action from Custom to Expand...
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2013-02-06
Tom Stellard
R600: Support for indirect addressing v4
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2013-01-23
Tom Stellard
R600: rework handling of the constants
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2012-12-11
Tom Stellard
Add R600 backend
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