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Migrate AArch64 except for TTI and AsmPrinter away from getSubtargetImpl.
[oota-llvm.git]
/
lib
/
Target
/
R600
/
R600Instructions.td
2015-01-21
Matt Arsenault
R600/SI: Custom lower fround
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2014-12-11
Matt Arsenault
R600/SI: Use unordered not equal instructions
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2014-11-26
Craig Topper
Replace neverHasSideEffects=1 with hasSideEffects=0...
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2014-11-14
Tom Stellard
R600/SI: Start implementing an assembler
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2014-11-13
Matt Arsenault
R600/SI: Fix fmin_legacy / fmax_legacy matching for SI
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2014-11-02
Matt Arsenault
R600: Don't unnecessarily repeat the register class
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2014-10-14
Jan Vesely
R600: FMA is VecALU only instruction
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2014-09-05
Jan Vesely
R600: Fix FROUND
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2014-07-24
Matt Arsenault
R600: Add FMA instructions for Evergreen
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2014-07-24
Matt Arsenault
R600: Match rcp node on pre-SI
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2014-07-11
Marek Olsak
R600/SI: fix shadow mapping for 1D and 2D array textures
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2014-06-24
Matt Arsenault
R600: Fix inconsistency in rsq instructions.
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2014-06-20
Tom Stellard
R600/SI: Add a pattern for f32 ftrunc
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2014-06-19
Matt Arsenault
R600/SI: Add intrinsics for various math instructions.
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2014-06-17
Tom Stellard
R600: Use LDS and vectors for private memory
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2014-06-13
Tom Stellard
R600: Remove AMDIL instruction and register definitions
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2014-06-11
Tom Stellard
R600: Set correct InstrItinClass for instructions using...
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2014-05-22
Matt Arsenault
R600: Expand mul24 for GPUs without it
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2014-05-22
Matt Arsenault
R600: Expand mad24 for GPUs without it
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2014-03-24
Tom Stellard
R600: Reorganize tablegen instruction definitions
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2014-03-17
Matt Arsenault
R600: Match sign_extend_inreg to BFE instructions
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2014-03-13
Tom Stellard
R600: LDS instructions shouldn't implicitly define...
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2014-02-26
Matt Arsenault
R600: Remove unnecessary build_vector pattern.
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2014-01-24
Alp Toker
Fix known typos
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2014-01-23
Tom Stellard
R600: Disable the BFE pattern
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2014-01-22
Tom Stellard
R600: Add some missing CF instruction definitions to...
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2014-01-22
Tom Stellard
R600: CF_PUSH is the same on Evergreen and Cayman
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2014-01-22
Tom Stellard
R600: MOVA is vector only
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2013-12-20
Tom Stellard
R600: Allow ftrunc
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2013-12-02
Vincent Lejeune
R600: Workaround for cayman loop bug
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2013-11-27
Tom Stellard
R600: Add support for ISD::FROUND
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2013-11-22
Tom Stellard
R600/SI: Fixing handling of condition codes
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2013-11-13
Tom Stellard
R600/SI: Add support for private address space load...
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2013-11-11
Vincent Lejeune
R600: Use function inputs to represent data stored...
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2013-10-13
Vincent Lejeune
R600: Clear the VPM bit of export instructions.
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2013-10-02
Vincent Lejeune
R600: Add a ldptr intrinsic to support MSAA.
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2013-10-01
Vincent Lejeune
R600: add a pass that merges clauses.
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2013-10-01
Vincent Lejeune
R600: Enable -verify-machineinstrs in some tests.
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2013-09-28
Tom Stellard
R600: Fix handling of NAN in comparison instructions
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2013-09-28
Tom Stellard
SelectionDAG: Try to expand all condition codes using...
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2013-09-06
Aaron Watry
R600: Add support for LDS atomic subtract
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2013-09-05
Tom Stellard
R600: Add support for local memory atomic add
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2013-09-04
Vincent Lejeune
R600: Use SchedModel enum for is{Trans,Vector}Only...
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2013-08-26
Tom Stellard
R600: Add support for i8 and i16 local memory loads
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2013-08-26
Tom Stellard
R600: Add support for i8 and i16 local memory stores
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2013-08-16
Tom Stellard
R600: Add support for i16 and i8 global stores
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2013-08-16
Tom Stellard
R600: Add support for v4i32 stores on Cayman
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2013-08-16
Tom Stellard
R600: Add IsExport bit to TableGen instruction definitions
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2013-08-16
Tom Stellard
R600: Change the RAT instruction assembly names so...
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2013-08-14
Tom Stellard
R600/SI: Handle MSAA texture targets
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2013-08-01
Tom Stellard
R600: Add 64-bit float load/store support
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2013-07-31
Tom Stellard
Revert "R600: Use SchedModel enum for is{Trans,Vector...
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2013-07-31
Vincent Lejeune
R600: Use SchedModel enum for is{Trans,Vector}Only...
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2013-07-31
Vincent Lejeune
R600: Remove predicated_break inst
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2013-07-23
Tom Stellard
R600: Treat CONSTANT_ADDRESS loads like GLOBAL_ADDRESS...
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2013-07-23
Tom Stellard
R600: Add support for 24-bit MAD instructions
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2013-07-23
Tom Stellard
R600: Add support for 24-bit MUL instructions
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2013-07-23
Tom Stellard
R600: Improve support for < 32-bit loads
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2013-07-23
Tom Stellard
R600: Use KCache for kernel arguments
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2013-07-23
Tom Stellard
R600: Clean up extended load patterns
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2013-07-19
Vincent Lejeune
R600: Don't emit empty then clause and use alu_pop_after
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2013-07-09
Vincent Lejeune
R600: Do not predicated basic block with multiple alu...
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2013-07-09
Vincent Lejeune
R600: Use DAG lowering pass to handle fcos/fsin
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2013-07-09
Vincent Lejeune
R600: Print Export Swizzle
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2013-06-29
Vincent Lejeune
R600: Support schedule and packetization of trans-only...
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2013-06-28
Tom Stellard
R600: Add local memory support via LDS
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2013-06-28
Tom Stellard
R600: Add support for GROUP_BARRIER instruction
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2013-06-28
Tom Stellard
R600: Add ALUInst bit to tablegen definitions v2
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2013-06-25
Tom Stellard
R600: Use new getNamedOperandIdx function generated...
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2013-06-25
Tom Stellard
R600: Add support for i32 loads from the constant addre...
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2013-06-24
Aaron Watry
R600: Fix spelling error in comment
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2013-06-17
Vincent Lejeune
R600: Properly set COUNT_3 bit in TEX clause initiating...
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2013-06-14
Tom Stellard
R600: Use correct encoding for Vertex Fetch instruction...
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2013-06-14
Tom Stellard
R600: Use EXPORT_RAT_INST_STORE_DWORD for stores on...
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2013-06-14
Tom Stellard
R600: Factor the instruction encoding out the RAT_WRITE...
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2013-06-14
Tom Stellard
R600: Move instruction encoding definitions into a...
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2013-06-07
Tom Stellard
R600: Rework subtarget info and remove AMDILDevice...
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2013-06-03
Vincent Lejeune
R600: Constraints input regs of interp_xy,_zw
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2013-05-20
Tom Stellard
R600: Swap the legality of rotl and rotr
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2013-05-17
Vincent Lejeune
R600: Relax some vector constraints on Dot4.
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2013-05-17
Vincent Lejeune
R600: Improve texture handling
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2013-05-17
Vincent Lejeune
R600: Rename 128 bit registers.
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2013-05-17
Vincent Lejeune
R600: prettier dump of clamp
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2013-05-10
Tom Stellard
R600: Remove AMDILPeeopholeOptimizer and replace optimi...
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2013-05-03
Tom Stellard
R600: BFI_INT is a vector-only instruction
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2013-05-03
Tom Stellard
R600: Add pattern for SHA-256 Ma function
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2013-05-02
Vincent Lejeune
R600: Improve asmPrint of ALU clause
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2013-05-02
Vincent Lejeune
R600: Prettier asmPrint of Alu
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2013-05-02
Tom Stellard
R600: Use new tablegen syntax for patterns
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2013-04-30
Vincent Lejeune
R600: use native for alu
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2013-04-30
Vincent Lejeune
R600: Rework Scheduling to handle difference between...
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2013-04-30
Vincent Lejeune
R600: Add a Bank Swizzle operand
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2013-04-30
Vincent Lejeune
R600: Turn TEX/VTX into native instructions
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2013-04-30
Vincent Lejeune
R600: Add FetchInst bit to instruction defs to denote...
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2013-04-30
Vincent Lejeune
R600: Clean up instruction class definitions
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2013-04-29
Tom Stellard
R600: Fix encoding of CF_END_{EG, R600} instructions
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2013-04-23
Vincent Lejeune
R600: Use .AMDGPU.config section to emit stacksize
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2013-04-23
Vincent Lejeune
R600: Add CF_END
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2013-04-19
Tom Stellard
R600: Add pattern for the BFI_INT instruction
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2013-04-17
Vincent Lejeune
R600: Make Export Instruction not duplicable
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