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Set REQUIRES shell on the test cases for r186044
[oota-llvm.git]
/
lib
/
Target
/
R600
/
R600Instructions.td
2013-07-09
Vincent Lejeune
R600: Do not predicated basic block with multiple alu...
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2013-07-09
Vincent Lejeune
R600: Use DAG lowering pass to handle fcos/fsin
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2013-07-09
Vincent Lejeune
R600: Print Export Swizzle
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2013-06-29
Vincent Lejeune
R600: Support schedule and packetization of trans-only...
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2013-06-28
Tom Stellard
R600: Add local memory support via LDS
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2013-06-28
Tom Stellard
R600: Add support for GROUP_BARRIER instruction
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2013-06-28
Tom Stellard
R600: Add ALUInst bit to tablegen definitions v2
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2013-06-25
Tom Stellard
R600: Use new getNamedOperandIdx function generated...
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2013-06-25
Tom Stellard
R600: Add support for i32 loads from the constant addre...
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2013-06-24
Aaron Watry
R600: Fix spelling error in comment
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2013-06-17
Vincent Lejeune
R600: Properly set COUNT_3 bit in TEX clause initiating...
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2013-06-14
Tom Stellard
R600: Use correct encoding for Vertex Fetch instruction...
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2013-06-14
Tom Stellard
R600: Use EXPORT_RAT_INST_STORE_DWORD for stores on...
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2013-06-14
Tom Stellard
R600: Factor the instruction encoding out the RAT_WRITE...
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2013-06-14
Tom Stellard
R600: Move instruction encoding definitions into a...
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2013-06-07
Tom Stellard
R600: Rework subtarget info and remove AMDILDevice...
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2013-06-03
Vincent Lejeune
R600: Constraints input regs of interp_xy,_zw
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2013-05-20
Tom Stellard
R600: Swap the legality of rotl and rotr
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2013-05-17
Vincent Lejeune
R600: Relax some vector constraints on Dot4.
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2013-05-17
Vincent Lejeune
R600: Improve texture handling
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2013-05-17
Vincent Lejeune
R600: Rename 128 bit registers.
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2013-05-17
Vincent Lejeune
R600: prettier dump of clamp
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2013-05-10
Tom Stellard
R600: Remove AMDILPeeopholeOptimizer and replace optimi...
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2013-05-03
Tom Stellard
R600: BFI_INT is a vector-only instruction
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2013-05-03
Tom Stellard
R600: Add pattern for SHA-256 Ma function
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2013-05-02
Vincent Lejeune
R600: Improve asmPrint of ALU clause
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2013-05-02
Vincent Lejeune
R600: Prettier asmPrint of Alu
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2013-05-02
Tom Stellard
R600: Use new tablegen syntax for patterns
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2013-04-30
Vincent Lejeune
R600: use native for alu
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2013-04-30
Vincent Lejeune
R600: Rework Scheduling to handle difference between...
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2013-04-30
Vincent Lejeune
R600: Add a Bank Swizzle operand
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2013-04-30
Vincent Lejeune
R600: Turn TEX/VTX into native instructions
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2013-04-30
Vincent Lejeune
R600: Add FetchInst bit to instruction defs to denote...
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2013-04-30
Vincent Lejeune
R600: Clean up instruction class definitions
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2013-04-29
Tom Stellard
R600: Fix encoding of CF_END_{EG, R600} instructions
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2013-04-23
Vincent Lejeune
R600: Use .AMDGPU.config section to emit stacksize
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2013-04-23
Vincent Lejeune
R600: Add CF_END
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2013-04-19
Tom Stellard
R600: Add pattern for the BFI_INT instruction
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2013-04-17
Vincent Lejeune
R600: Make Export Instruction not duplicable
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2013-04-17
Vincent Lejeune
R600: Export is emitted as a CF_NATIVE inst
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2013-04-10
Michel Danzer
R600/SI: Add pattern for AMDGPUurecip
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2013-04-08
Vincent Lejeune
R600: Control Flow support for pre EG gen
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2013-04-01
Vincent Lejeune
R600: Add support for native control flow
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2013-04-01
Vincent Lejeune
R600: Emit CF_ALU and use true kcache register.
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2013-03-31
Vincent Lejeune
R600: Emit native instructions for tex
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2013-03-22
Michel Danzer
R600: Use legacy (0 * anything = 0) MUL instructions...
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2013-03-18
Christian Konig
R600/SI: add float vector types
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2013-03-11
Vincent Lejeune
R600: Fix JUMP handling so that MachineInstr verificati...
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2013-03-08
Tom Stellard
R600: Improve custom lowering of select_cc
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2013-03-05
Vincent Lejeune
R600: Remove LowerConstCopyPass and lower CONST_COPY...
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2013-03-05
Vincent Lejeune
R600: CONST_ADDRESS node is not marked as mayLoad anymore
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2013-03-05
Vincent Lejeune
R600: Use MUL_IEEE for trig/fdiv intrinsic
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2013-03-05
Vincent Lejeune
R600: Add support for indirect addressing of non defaul...
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2013-02-21
Tom Stellard
R600: Fix for Unigine when MachineSched is enabled
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2013-02-18
Vincent Lejeune
R600/SI: Use MULADD_IEEE/V_MAD_F32 instruction for...
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2013-02-18
Vincent Lejeune
R600: Support for TBO
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2013-02-14
Vincent Lejeune
R600: Export instructions are no longer terminator
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2013-02-14
Vincent Lejeune
R600: Fold zero/one in export instructions
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2013-02-13
Tom Stellard
R600: Add support for 128-bit parameters
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2013-02-12
Michel Danzer
R600: Fix regression with shadow array sampler on pre...
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2013-02-10
Vincent Lejeune
Test Commit - Remove some trailing whitespace in R600In...
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2013-02-07
Tom Stellard
R600/SI: Use proper instructions for array/shadow samplers.
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2013-02-07
Tom Stellard
R600: Consolidate sub register indices.
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2013-02-07
Tom Stellard
R600: Add support for SET*_DX10 instructions
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2013-02-07
Tom Stellard
R600: Fix assembly name for SETGT_INT
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2013-02-06
Tom Stellard
R600: Support for indirect addressing v4
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2013-02-05
Jakob Stoklund Olesen
Don't use MRI liveouts in R600.
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2013-02-05
Tom Stellard
R600: improve inputs/interpolation handling
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2013-01-31
Tom Stellard
R600: Make store_dummy intrinsic more general by passin...
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2013-01-23
Tom Stellard
R600: Add a llvm.R600.store.swizzle intrinsics
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2013-01-23
Tom Stellard
R600: Simplify stream outputs intrinsic
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2013-01-23
Tom Stellard
R600: rework handling of the constants
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2013-01-23
Tom Stellard
R600: Add a CONST_ADDRESS node to model constant buf...
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2013-01-23
Tom Stellard
R600: Factorise VTX_WORD0 and VTX_WORD1 in tblgen def
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2013-01-21
Tom Stellard
R600/SI: Use unnormalized coordinates for sampling...
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2012-12-21
Tom Stellard
R600: Fix MAX_UINT definition
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2012-12-21
Tom Stellard
R600: Add SHADOWCUBE to TEX_SHADOW pattern
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2012-12-19
Tom Stellard
R600: New control flow for SI v2
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2012-12-11
Tom Stellard
Add R600 backend
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