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CodeGen: convert CCState interface to using ArrayRefs
[oota-llvm.git]
/
lib
/
Target
/
R600
/
SIISelLowering.cpp
2015-02-21
Tim Northover
CodeGen: convert CCState interface to using ArrayRefs
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2015-02-20
Matt Arsenault
R600/SI: Remove v_sub_f64 pseudo
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2015-02-20
Matt Arsenault
R600: Use new fmad node.
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2015-02-17
Benjamin Kramer
Prefer SmallVector::append/insert over push_back loops.
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2015-02-16
Andrew Trick
AArch64: Safely handle the incoming sret call argument.
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2015-02-14
Matt Arsenault
R600/SI: Implement correct f64 fdiv
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2015-02-13
Matt Arsenault
R600/SI: Allow f64 inline immediates in i64 operands
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2015-02-11
Tom Stellard
R600/SI: Add soffset operand to mubuf addr64 instruction
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2015-02-04
Tom Stellard
R600/SI: Expand misaligned 16-bit memory accesses
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2015-02-04
Tom Stellard
R600/SI: Make more store operations legal
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2015-02-02
Tom Stellard
R600/SI: 64-bit and larger memory access must be at...
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2015-01-30
Eric Christopher
Reuse a bunch of cached subtargets and remove getSubtar...
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2015-01-29
Matt Arsenault
R600/SI: Implement enableAggressiveFMAFusion
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2015-01-29
Matt Arsenault
R600/SI: Add subtarget feature for if f32 fma is fast
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2015-01-20
Tom Stellard
R600/SI: Add subtarget feature to enable VGPR spilling...
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2015-01-14
Matt Arsenault
R600/SI: Fix bad code with unaligned byte vector loads
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2015-01-14
Matt Arsenault
Implement new way of expanding extloads.
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2015-01-13
Tom Stellard
R600/SI: Add pattern for bitcasting fp immediates to...
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2015-01-12
Matt Arsenault
R600/SI: Remove redundant setting expand on f64 vectors
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2015-01-12
Tom Stellard
R600/SI: Use RegisterOperands to specify which operands...
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2015-01-08
Tom Stellard
R600/SI: Remove SIISelLowering::legalizeOperands()
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2015-01-08
Ahmed Bougacha
[SelectionDAG] Allow targets to specify legality of...
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2015-01-07
Tom Stellard
R600/SI: Remove VReg_32 register class
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2015-01-06
Matt Arsenault
R600/SI: Add combine for isinfinite pattern
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2015-01-06
Matt Arsenault
R600/SI: Pattern match isinf to v_cmp_class instructions
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2015-01-06
Matt Arsenault
R600/SI: Add basic DAG combines for fp_class
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2014-12-21
Matt Arsenault
Enable (sext x) == C --> x == (trunc C) combine
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2014-12-17
Matt Arsenault
R600/SI: Fix f64 inline immediates
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2014-12-12
Matt Arsenault
R600/SI: Don't promote f32 select to i32
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2014-12-11
Matt Arsenault
R600/SI: Use unordered equal instructions
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2014-12-11
Matt Arsenault
R600/SI: Make more unordered comparisons legal
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2014-12-11
Matt Arsenault
R600/SI: Use unordered not equal instructions
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2014-12-10
Marek Olsak
R600/SI: Use getTargetConstant in AdjustRegClass
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2014-12-07
Marek Olsak
R600/SI: Set 20-bit immediate byte offset for SMRD...
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2014-12-02
Tom Stellard
R600/SI: Set correct number of user sgprs for HSA runtime
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2014-12-02
Tom Stellard
R600/SI: Set the ATC bit on all resource descriptors...
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2014-11-28
Matt Arsenault
R600/SI: Fix assertion on sign extend of 3 vectors
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2014-11-21
Tom Stellard
R600/SI: Emit s_mov_b32 m0, -1 before every DS instruction
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2014-11-18
Tom Stellard
R600/SI: Make sure resource descriptors are always...
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2014-11-16
Craig Topper
Convert some EVTs to MVTs where only a SimpleValueType...
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2014-11-14
Matt Arsenault
R600/SI: Combine min3/max3 instructions
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2014-11-14
Matt Arsenault
R600/SI: Use S_BFE_I64 for 64-bit sext_inreg
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2014-11-13
Matt Arsenault
R600/SI: Get rid of FCLAMP_SI pseudo
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2014-11-05
Matt Arsenault
R600/SI: Move all rsrc building functions to SIISelLowering
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2014-11-05
Matt Arsenault
R600/SI: Remove SI_ADDR64_RSRC
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2014-11-02
Matt Arsenault
R600/SI: Use REG_SEQUENCE instead of INSERT_SUBREGs
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2014-10-21
Matt Arsenault
Add minnum / maxnum codegen
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2014-10-21
Matt Arsenault
R600/SI: Add pattern for bswap
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2014-10-17
Matt Arsenault
R600/SI: Remove SI_BUFFER_RSRC pseudo
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2014-10-14
Jan Vesely
Reapply "R600: Add new intrinsic to read work dimensions"
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2014-10-14
Rafael Espindola
Revert "R600: Add new intrinsic to read work dimensions"
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2014-10-14
Jan Vesely
R600: Add new intrinsic to read work dimensions
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2014-10-09
Tom Stellard
R600/SI: Legalize CopyToReg during instruction selection
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2014-10-09
Tom Stellard
R600/SI: Legalize INSERT_SUBREG instructions during...
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2014-10-03
Matt Arsenault
R600/SI: Custom lower f64 -> i64 conversions
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2014-09-29
Matt Arsenault
R600/SI: Also fix fsub + fadd a, a to mad combines
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2014-09-29
Matt Arsenault
R600/SI: Fix using mad with multiplies by 2
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2014-09-26
Matt Arsenault
R600/SI: Partially move operand legalization to post...
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2014-09-26
Matt Arsenault
R600/SI: Remove apparently dead code in legalizeOperands
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2014-09-23
Tom Stellard
R600/SI: Clean up checks for legality of immediate...
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2014-09-22
Tom Stellard
R600/SI: Add enums for some hard-coded values
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2014-09-17
Matt Arsenault
R600/SI: Remove promotion of instructions to e64 forms.
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2014-09-10
Matt Arsenault
R600/SI: Fix losing chain when fixing reg class of...
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2014-09-08
Matt Arsenault
R600/SI: Fix assertion from copying a TargetGlobalAddress
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2014-09-08
Matt Arsenault
R600/SI: Replace LDS atomics with no return versions
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2014-08-29
Matt Arsenault
R600/SI: Use mad for fsub + fmul
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2014-08-27
Alexey Samsonov
Use BitVector instead of int in R600 SIISelLowering.
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2014-08-22
Tom Stellard
R600/SI: Wrap local memory pointer in AssertZExt on SI
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2014-08-21
Tom Stellard
R600/SI: Make sure SCRATCH_WAVE_OFFSET is added as...
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2014-08-18
Aaron Ballman
Silencing an MSVC warning about loop variable conflicti...
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2014-08-15
Matt Arsenault
R600/SI: Move all fabs / fneg handling to patterns
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2014-08-15
Matt Arsenault
R600/SI: Use source modifiers for f64 fneg
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2014-08-15
Matt Arsenault
R600/SI: Use source modifier for f64 fabs
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2014-08-15
Matt Arsenault
R600/SI: Fix offset folding in some cases with shifted...
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2014-08-15
Matt Arsenault
R600/SI: Implement isLegalAddressingMode
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2014-08-09
Tom Stellard
R600/SI: Custom lower CONCAT_VECTORS
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2014-08-06
Eric Christopher
Remove the target machine from CCState. Previously...
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2014-08-04
Eric Christopher
Remove the TargetMachine forwards for TargetSubtargetIn...
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2014-08-02
Matt Arsenault
R600/SI: Fix formatting.
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2014-08-01
Chandler Carruth
[SDAG] MorphNodeTo recursively deletes dead operands...
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2014-08-01
Tom Stellard
R600/SI: Do abs/neg folding with ComplexPatterns
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2014-07-28
Matt Arsenault
R600/SI: Implement getOptimalMemOpType
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2014-07-28
Matt Arsenault
R600/SI: Make argument loads invariant
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2014-07-27
Matt Arsenault
Add alignment value to allowsUnalignedMemoryAccess
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2014-07-26
Matt Arsenault
R600: Move intrinsic lowering to separate functions
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2014-07-24
Matt Arsenault
R600: Add new functions for splitting vector loads...
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2014-07-21
Tom Stellard
R600/SI: Clean up some of the unused REGISTER_{LOAD...
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2014-07-21
Tom Stellard
R600/SI: Use scratch memory for large private arrays
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2014-07-21
Tom Stellard
R600/SI: Store constant initializer data in constant...
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2014-07-20
NAKAMURA Takumi
SIISelLowering.cpp: Define _USE_MATH_DEFINES to let...
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2014-07-20
Matt Arsenault
R600/SI: Remove dead code and add missing tests.
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2014-07-19
Matt Arsenault
R600/SI: implement range reduction for sin/cos
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2014-07-15
Matt Arsenault
R600/SI: Allow using f32 rcp / rsq when denormals not...
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2014-07-15
Matt Arsenault
R600/SI: Fix select on i1
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2014-07-15
Matt Arsenault
R600/SI: Implement less wrong f32 fdiv
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2014-07-13
Matt Arsenault
R600: Make ShaderType private
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2014-07-10
Jan Vesely
R600: Implement float to long/ulong
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2014-07-07
Matt Arsenault
R600: Fix mishandling of load / store chains.
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2014-07-03
Chandler Carruth
[codegen,aarch64] Add a target hook to the code generat...
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2014-07-02
Tom Stellard
R600: Promote i64 loads to v2i32
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