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R600/SI: Expand misaligned 16-bit memory accesses
[oota-llvm.git]
/
lib
/
Target
/
R600
/
SIInstrInfo.td
2015-02-03
Marek Olsak
R600/SI: Rewrite VOP1InstSI to contain a pseudo and...
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2015-02-03
Marek Olsak
R600/SI: Fix B64 VALU shifts on VI
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2015-02-03
Marek Olsak
R600/SI: Don't generate non-existent LSHL, LSHR, ASHR...
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2015-02-03
Marek Olsak
R600/SI: Remove VOP2_REV definitions from target-specif...
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2015-02-03
Marek Olsak
R600/SI: Trivial instruction definition corrections...
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2015-01-30
Eric Christopher
Reuse a bunch of cached subtargets and remove getSubtar...
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2015-01-27
Marek Olsak
R600/SI: Don't set patterns for chip-specific instructi...
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2015-01-27
Marek Olsak
R600/SI: Add VI versions of LDS atomics
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2015-01-27
Marek Olsak
R600/SI: Add VI versions of MUBUF atomics
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2015-01-27
Marek Olsak
R600/SI: Add VI versions of MUBUF loads and stores
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2015-01-27
Marek Olsak
R600/SI: Add pseudos for MUBUF loads and stores
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2015-01-15
Matt Arsenault
R600/SI: Fix trailing comma with modifiers
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2015-01-15
Marek Olsak
R600/SI: Unify VOP2 instructions which are VOP3-only...
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2015-01-15
Marek Olsak
R600/SI: Add V_READLANE_B32 and V_WRITELANE_B32 for VI
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2015-01-15
Marek Olsak
R600/SI: Don't shrink instructions whose e32 encoding...
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2015-01-14
Tom Stellard
R600/SI: Spill VGPRs to scratch space for compute shaders
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2015-01-13
Tom Stellard
R600/SI: Add pattern for bitcasting fp immediates to...
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2015-01-12
Tom Stellard
R600/SI: Use RegisterOperands to specify which operands...
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2015-01-07
Tom Stellard
R600/SI: Remove VReg_32 register class
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2015-01-06
Matt Arsenault
R600/SI: Add class intrinsic
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2014-12-19
Tom Stellard
R600/SI: Make sure non-inline constants aren't folded...
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2014-12-17
Matt Arsenault
R600/SI: Fix f64 inline immediates
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2014-12-09
Tom Stellard
R600/SI: Set MayStore = 0 on MUBUF loads
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2014-12-09
Tom Stellard
R600/SI: Move setting of the lds bit to the base MUBUF...
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2014-12-07
Marek Olsak
R600/SI: Set 20-bit immediate byte offset for SMRD...
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2014-12-07
Marek Olsak
R600/SI: Add VI instructions
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2014-12-03
Matt Arsenault
R600/SI: Remove i1 pseudo VALU ops
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2014-12-01
Matt Arsenault
R600/SI: Various instruction format bit test cleanups
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2014-11-21
Tom Stellard
R600/SI: Emit s_mov_b32 m0, -1 before every DS instruction
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2014-11-18
Matt Arsenault
R600/SI: Set hasSideEffects = 0 on load and store instr...
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2014-11-14
Matt Arsenault
R600/SI: Use S_BFE_I64 for 64-bit sext_inreg
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2014-11-13
Matt Arsenault
R600/SI: Use s_movk_i32
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2014-11-13
Matt Arsenault
R600/SI: Fix definition for s_cselect_b32
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2014-11-13
Matt Arsenault
R600/SI: Get rid of FCLAMP_SI pseudo
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2014-11-05
Matt Arsenault
R600/SI: Fix omod display for VOP3b
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2014-11-05
Tom Stellard
R600/SI: Change all instruction assembly names to lower...
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2014-11-04
Matt Arsenault
R600/SI: Rename div_scale dest operands to match docume...
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2014-10-10
Matt Arsenault
R600/SI: Change how DS offsets are printed
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2014-10-07
Tom Stellard
R600/SI: Refactor VOP3 instruction defs
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2014-10-07
Tom Stellard
R600/SI: Refactor VOPC instruction defs
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2014-10-07
Tom Stellard
R600/SI: Refactor VOP2 instruction defs
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2014-10-07
Tom Stellard
R600/SI: Refactor VOP1 instruction defs
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2014-10-01
Tom Stellard
R600/SI: Add a generic pseudo EXP instruction
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2014-10-01
Tom Stellard
R600/SI: Add generic pseudo MTBUF instructions
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2014-10-01
Tom Stellard
R600/SI: Add generic pseudo SMRD instructions
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2014-09-30
Matt Arsenault
R600/SI: Fix printing of clamp and omod
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2014-09-30
Matt Arsenault
R600/SI: Update VOP3b to not include obsolete operands
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2014-09-25
Tom Stellard
R600/SI: Add support for global atomic add
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2014-09-23
Tom Stellard
R600/SI: Clean up checks for legality of immediate...
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2014-09-22
Tom Stellard
Revert "R600/SI: Add support for global atomic add"
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2014-09-22
Tom Stellard
R600/SI: Add support for global atomic add
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2014-09-15
Matt Arsenault
R600/SI: Add preliminary support for flat address space
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2014-09-08
Matt Arsenault
R600/SI: Replace LDS atomics with no return versions
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2014-09-08
Matt Arsenault
R600/SI: Add InstrMapping for noret atomics.
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2014-08-29
Matt Arsenault
R600/SI: Use mad for fsub + fmul
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2014-08-22
Tom Stellard
R600/SI: Use READ2/WRITE2 instructions for 64-bit mem...
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2014-08-22
Tom Stellard
R600/SI: Use a ComplexPattern for DS loads and stores
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2014-08-22
Tom Stellard
R600/SI: Use correct helper class for DS_WRITE2 instruc...
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2014-08-11
Tom Stellard
R600/SI: Add a ComplexPattern for selecting MUBUF _OFFS...
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2014-08-11
Tom Stellard
R600/SI: Add an _OFFEN variant MUBUF_STORE_* and use...
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2014-08-11
Tom Stellard
R600/SI: Clear lds bit on MUBUF instructions used for...
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2014-08-05
Tom Stellard
R600/SI: Update MUBUF assembly string to match AMD...
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2014-08-04
Eric Christopher
Remove the TargetMachine forwards for TargetSubtargetIn...
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2014-08-04
Matt Arsenault
R600/SI: Fix definitions for ds_read2 / ds_write2 instr...
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2014-08-03
Matt Arsenault
R600/SI: Fix extra whitespace in asm str
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2014-08-01
Matt Arsenault
R600/SI: Don't display GDS bit for read2
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2014-08-01
Tom Stellard
R600/SI: Do abs/neg folding with ComplexPatterns
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2014-07-21
Tom Stellard
R600/SI: Refactor VOP3 instruction definitions
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2014-07-21
Tom Stellard
R600/SI: Initailize encoding fields of unused VOP3...
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2014-07-21
Tom Stellard
R600/SI: Initialize unused VOP3 sources to 0 instead...
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2014-07-21
Tom Stellard
R600/SI: Add instruction shrinking pass
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2014-07-21
Tom Stellard
R600/SI: VOPC instructions explicitly define VCC
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2014-07-21
Tom Stellard
R600/SI: Use scratch memory for large private arrays
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2014-07-21
Tom Stellard
R600/SI: Remove vaddr operand from BUFFER_LOAD_*_OFFSET...
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2014-07-21
Tom Stellard
R600/SI: Store constant initializer data in constant...
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2014-07-21
Tom Stellard
R600/SI: Use a custom encoding method for simm16 in...
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2014-07-02
Tom Stellard
R600/SI: Use a ComplexPattern for ADDR64 addressing...
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2014-06-24
Tom Stellard
R600/SI: Use a ComplexPattern for MUBUF stores
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2014-06-23
Matt Arsenault
R600/SI: Fix div_scale intrinsic.
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2014-06-18
Marek Olsak
R600/SI: add gather4 and getlod intrinsics (v3)
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2014-06-18
Matt Arsenault
R600/SI: Prettier operand printing for 64-bit ops.
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2014-06-18
Matt Arsenault
R600/SI: Comparisons set vcc.
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2014-06-17
Tom Stellard
R600/SI: Make sure target flags are set on pseudo VOP3...
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2014-06-12
Matt Arsenault
R600/SI: Use a register set to -1 for data0 on ds_inc...
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2014-06-11
Matt Arsenault
R600/SI: Add common 64-bit LDS atomics
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2014-06-11
Matt Arsenault
R600/SI: Add instruction definitions for more LDS ops
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2014-06-10
Matt Arsenault
R600/SI: Implement i64 ctpop
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2014-06-09
Matt Arsenault
R600/SI: Rename VOP3 helper class to be more general
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2014-05-16
Tom Stellard
R600/SI: Refactor the VOP3_32 tablegen class
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2014-05-10
Vincent Lejeune
R600/SI: Prettier display of input modifiers
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2014-05-09
Tom Stellard
R600/SI: Fix SMRD pattern for offsets > 32 bits
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2014-05-01
Matt Arsenault
R600/SI: Fix verifier error with pseudo store instructions.
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2014-04-17
Tom Stellard
R600/SI: Stop using i128 as the resource descriptor...
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2014-04-15
Matt Arsenault
R600/SI: Print more immediates in hex format
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2014-04-11
Matt Arsenault
R600/SI: Refactor SOPC classes slightly.
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2014-04-03
Tom Stellard
R600/SI: Lower 64-bit immediates using REG_SEQUENCE
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2014-03-19
Matt Arsenault
R600/SI: Add unused LDS 2 form instructions.
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2014-03-19
Matt Arsenault
R600/SI: Match i16 immediate offset of LDS instructions.
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2014-03-19
Matt Arsenault
R600/SI: Don't display the GDS bit.
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2014-03-19
Matt Arsenault
R600/SI: Merge offset0 and offset1 fields for single...
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