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IR: Rewrite ConstantUniqueMap
[oota-llvm.git]
/
lib
/
Target
/
R600
/
SIInstructions.td
2014-08-15
Matt Arsenault
R600/SI: Move all fabs / fneg handling to patterns
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2014-08-15
Matt Arsenault
R600/SI: Use source modifiers for f64 fneg
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2014-08-15
Matt Arsenault
R600/SI: Refactor fneg / fabs patterns
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2014-08-15
Matt Arsenault
R600/SI: Add intrinsic for ldexp
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2014-08-11
Tom Stellard
R600/SI: Add an _OFFEN variant MUBUF_STORE_* and use...
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2014-08-05
Matt Arsenault
R600/SI: Add definitions for ds_read2st64_ / ds_write2st64_
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2014-08-04
Matt Arsenault
R600/SI: Fix definitions for ds_read2 / ds_write2 instr...
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2014-08-01
Tom Stellard
R600/SI: Do abs/neg folding with ComplexPatterns
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2014-07-30
Matt Arsenault
R600/SI: Remove redundant setting of bits on instructions.
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2014-07-21
Tom Stellard
R600/SI: Use scratch memory for large private arrays
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2014-07-21
Tom Stellard
R600/SI: Remove vaddr operand from BUFFER_LOAD_*_OFFSET...
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2014-07-21
Tom Stellard
R600/SI: Store constant initializer data in constant...
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2014-07-21
Tom Stellard
R600/SI: Add isCFDepth0 Predicate to SALU addc pattern
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2014-07-21
Tom Stellard
R600/SI: Use VALU for i1 XOR
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2014-07-21
Tom Stellard
R600/SI: Use a custom encoding method for simm16 in...
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2014-07-21
Tom Stellard
R600/SI: Rename SOPP operands to match the encoding...
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2014-07-19
Matt Arsenault
R600/SI: implement range reduction for sin/cos
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2014-07-17
Tim Northover
CodeGen: extend f16 conversions to permit types > float.
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2014-07-15
Matt Arsenault
R600/SI: Allow using f32 rcp / rsq when denormals not...
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2014-07-15
Matt Arsenault
R600/SI: Implement less wrong f32 fdiv
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2014-07-11
Marek Olsak
R600/SI: Use i32 vectors for resources and samplers
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2014-07-11
Marek Olsak
R600/SI: add sample and image intrinsics exposing all...
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2014-07-10
Matt Arsenault
R600/SI: Add support for llvm.convert.{to|from}.fp16
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2014-07-02
Tom Stellard
R600/SI: Use a ComplexPattern for ADDR64 addressing...
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2014-07-02
Tom Stellard
R600: Promote i64 loads to v2i32
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2014-07-02
Tom Stellard
R600/SI: Add verifier check for immediates in register...
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2014-06-24
Tom Stellard
R600/SI: Use a ComplexPattern for MUBUF stores
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2014-06-24
Tom Stellard
R600: Promote i64 stores to v2i32
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2014-06-24
Matt Arsenault
R600: Fix inconsistency in rsq instructions.
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2014-06-24
Matt Arsenault
R600/SI: Move pattern to instruction definition
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2014-06-23
Matt Arsenault
R600/SI: Fix div_scale intrinsic.
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2014-06-20
Tom Stellard
R600/SI: Add patterns for ctpop inside a branch
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2014-06-20
Tom Stellard
R600/SI: Add a pattern for f32 ftrunc
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2014-06-20
Tom Stellard
R600/SI: Add a VALU pattern for i64 xor
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2014-06-19
Matt Arsenault
R600/SI: Add intrinsics for various math instructions.
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2014-06-18
Marek Olsak
R600/SI: add gather4 and getlod intrinsics (v3)
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2014-06-18
Matt Arsenault
R600/SI: Add intrinsics for brev instructions
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2014-06-18
Matt Arsenault
R600/SI: Comparisons set vcc.
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2014-06-17
Matt Arsenault
R600/SI: Match cttz_zero_undef
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2014-06-17
Matt Arsenault
R600/SI: Match ctlz_zero_undef
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2014-06-17
Tom Stellard
R600: Use LDS and vectors for private memory
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2014-06-17
Tom Stellard
R600/SI: Add a pattern for llvm.AMDGPU.barrier.global
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2014-06-13
Tom Stellard
R600: Remove AMDIL instruction and register definitions
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2014-06-12
Matt Arsenault
R600: Mostly remove remaining AMDIL intrinsics.
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2014-06-12
Matt Arsenault
R600/SI: Use a register set to -1 for data0 on ds_inc...
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2014-06-11
Matt Arsenault
R600/SI: Fix bitcast between v2i32 and f64
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2014-06-11
Matt Arsenault
R600/SI: Update place using old subtarget predicate
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2014-06-11
Matt Arsenault
R600/SI: Add common 64-bit LDS atomics
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2014-06-11
Matt Arsenault
R600/SI: Add instruction definitions for 64-bit LDS...
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2014-06-11
Matt Arsenault
R600/SI: Add 32-bit LDS atomic cmpxchg
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2014-06-11
Matt Arsenault
R600/SI: Use LDS atomic inc / dec
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2014-06-11
Matt Arsenault
R600/SI: Add other LDS atomic operations
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2014-06-11
Matt Arsenault
R600/SI: Add instruction definitions for more LDS ops
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2014-06-11
Matt Arsenault
R600/SI: Fix backwards names for local atomic instructions.
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2014-06-11
Matt Arsenault
R600/SI: Refactor local atomics.
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2014-06-11
Matt Arsenault
R600/SI: Use v_cvt_f32_ubyte* instructions
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2014-06-11
Matt Arsenault
R600/SI: Fix selection failure on scalar_to_vector
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2014-06-10
Tom Stellard
R600/SI: Fix a crash when spilling SGPRs
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2014-06-10
Matt Arsenault
R600/SI: Implement i64 ctpop
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2014-06-10
Matt Arsenault
R600/SI: Use bcnt instruction for ctpop
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2014-06-10
Matt Arsenault
R600: Handle fcopysign
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2014-06-10
Matt Arsenault
R600/SI: Handle sign_extend and zero_extend to i64...
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2014-06-09
Matt Arsenault
R600/SI: Rename VOP3 helper class to be more general
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2014-06-09
Matt Arsenault
R600/SI: Keep 64-bit not on SALU
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2014-06-05
Matt Arsenault
R600/SI: Match rsq instructions
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2014-05-31
Matt Arsenault
R600/SI: Remove redundant patterns
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2014-05-31
Matt Arsenault
R600/SI: Fix [s|u]int_to_fp for i1
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2014-05-29
Matt Arsenault
R600/SI: Fix pattern variable names.
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2014-05-22
Matt Arsenault
R600: Add intrinsics for mad24
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2014-05-22
Matt Arsenault
R600/SI: Move instruction pattern to instruction definition
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2014-05-22
Matt Arsenault
R600/SI: Match fp_to_uint / uint_to_fp for f64
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2014-05-16
Tom Stellard
R600/SI: Refactor the VOP3_32 tablegen class
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2014-05-16
Tom Stellard
R600/SI: Add a PredicateControl class for managing...
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2014-05-16
Tom Stellard
R600/SI: Move tablegen patterns away from instruction...
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2014-05-16
Tom Stellard
R600/SI: Remove unused instruction
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2014-05-16
Tom Stellard
R600/SI: Promote f32 SELECT to i32
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2014-05-16
Tom Stellard
R600/SI: Remove duplicate pattern
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2014-05-15
Tom Stellard
R600/SI: Stop using VSrc_* as the default register...
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2014-05-15
Tom Stellard
R600/SI: Use VALU instructions for i1 ops
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2014-05-10
Vincent Lejeune
R600/SI: Prettier display of input modifiers
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2014-05-10
Vincent Lejeune
R600/SI: Use pseudo instruction for fabs/clamp/fneg
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2014-05-09
Tom Stellard
R600/SI: Fix SMRD pattern for offsets > 32 bits
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2014-05-02
Tom Stellard
R600/SI: Only create one instruction when spilling...
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2014-04-30
Tom Stellard
R600/SI: Use VALU instructions for copying i1 values
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2014-04-29
Tom Stellard
R600/SI: Custom lower SI_IF and SI_ELSE to avoid machin...
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2014-04-29
Tom Stellard
R600/SI: Only select SALU instructions in the entry...
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2014-04-22
Tom Stellard
R600/SI: Reorganize SIInstructions.td
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2014-04-22
Matt Arsenault
R600: Make sign_extend_inreg legal.
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2014-04-18
Matt Arsenault
R600/SI: Match sign_extend_inreg to s_sext_i32_i8 and...
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2014-04-17
Tom Stellard
R600/SI: Stop using i128 as the resource descriptor...
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2014-04-17
Matt Arsenault
R600/SI: f64 frint is legal on CI
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2014-04-11
Matt Arsenault
R600/SI: Refactor SOPC classes slightly.
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2014-04-09
Matt Arsenault
R600/SI: Match not instruction.
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2014-04-07
Tom Stellard
R600: Match 24-bit arithmetic patterns in a Target...
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2014-04-03
Tom Stellard
R600/SI: Lower 64-bit immediates using REG_SEQUENCE
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2014-03-31
Matt Arsenault
R600/SI: Remove leftover pattern splitting 64-bit ors.
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2014-03-31
Matt Arsenault
R600: Add target nodes for BFM and BFI
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2014-03-31
Tom Stellard
R600/SI: Lower i64 SELECT by bitcasting to a vector...
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2014-03-24
Matt Arsenault
R600/SI: Fix 64-bit bit ops that require the VALU.
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2014-03-24
Tom Stellard
R600/SI: Promote fp64 SELECT to i64
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