Use SmallVectorImpl::iterator/const_iterator instead of SmallVector to avoid specifyi...
[oota-llvm.git] / lib / Target / R600 /
2013-07-03 Craig TopperUse SmallVectorImpl::iterator/const_iterator instead...
2013-07-02 Rafael EspindolaRemove address spaces from MC.
2013-07-01 Chad RosierAdd a newline.
2013-06-30 Vincent LejeuneR600: Fix an unitialized variable in R600InstrInfo.cpp
2013-06-29 Benjamin KramerR600: Unbreak GCC build.
2013-06-29 Vincent LejeuneR600: Support schedule and packetization of trans-only...
2013-06-29 Vincent LejeuneR600: Bank Swizzle now display SCL equivalent
2013-06-28 Tom StellardR600/SI: Add processor types for each CIK variant
2013-06-28 Tom StellardR600: Add local memory support via LDS
2013-06-28 Tom StellardR600: Add support for GROUP_BARRIER instruction
2013-06-28 Tom StellardR600: Add ALUInst bit to tablegen definitions v2
2013-06-25 Tom StellardR600: Use new getNamedOperandIdx function generated...
2013-06-25 Aaron WatryR600: Consolidate expansion of v2i32/v4i32 ops for...
2013-06-25 Aaron WatryR600/SI: Expand xor v2i32/v4i32
2013-06-25 Aaron WatryR600/SI: Expand urem of v2i32/v4i32 for SI
2013-06-25 Aaron WatryR600/SI: Expand udiv v[24]i32 for SI and v2i32 for EG
2013-06-25 Aaron WatryR600/SI: Expand ashr of v2i32/v4i32 for SI
2013-06-25 Aaron WatryR600/SI: Expand srl of v2i32/v4i32 for SI
2013-06-25 Aaron WatryR600/SI: Expand shl of v2i32/v4i32 for SI
2013-06-25 Aaron WatryR600/SI: Expand or of v2i32/v4i32 for SI
2013-06-25 Aaron WatryR600/SI: Expand mul of v2i32/v4i32 for SI
2013-06-25 Aaron WatryR600/SI: Expand and of v2i32/v4i32 for SI
2013-06-25 Tom StellardR600/SI: Report unaligned memory accesses as legal...
2013-06-25 Tom StellardR600: Add support for i32 loads from the constant addre...
2013-06-25 Tom StellardR600/SI: Add support for v4i32 and v4f32 kernel args
2013-06-25 Tom StellardR600: Fix typo in R600Schedule.td
2013-06-24 Aaron WatryR600: Fix spelling error in comment
2013-06-20 Tom StellardR600/SI: Expand sub for v2i32 and v4i32 for SI
2013-06-20 Tom StellardR600/SI: Expand add for v2i32 and v4i32
2013-06-20 Tom StellardR600: Expand v2i32 load/store instead of custom lowering
2013-06-19 Bill WendlingAccess the TargetLoweringInfo from the TargetMachine...
2013-06-19 Matt ArsenaultMove StructurizeCFG out of R600 to generic Transforms.
2013-06-18 Matt ArsenaultUse GetUnderlyingObject instead of custom function
2013-06-18 Bill WendlingRemove dead prototype.
2013-06-17 Vincent LejeuneR600: PV stores Reg id, not index
2013-06-17 Vincent LejeuneR600: Properly set COUNT_3 bit in TEX clause initiating...
2013-06-15 Tom StellardR600: Add SI load support for v[24]i32 and store for...
2013-06-14 Tom StellardR600: Use correct encoding for Vertex Fetch instruction...
2013-06-14 Tom StellardR600: Use EXPORT_RAT_INST_STORE_DWORD for stores on...
2013-06-14 Tom StellardR600: Factor the instruction encoding out the RAT_WRITE...
2013-06-14 Tom StellardR600: Move instruction encoding definitions into a...
2013-06-13 Tom StellardR600: Don't try to fix reg class when copying IMPLICIT_...
2013-06-11 Benjamin KramerR600: Make helper functions static.
2013-06-07 Vincent LejeuneR600: Use a refined heuristic to choose when switching...
2013-06-07 Vincent LejeuneR600: Anti dep better handled in tex clause
2013-06-07 Tom StellardR600: Fix calculation of stack offset in AMDGPUFrameLow...
2013-06-07 Tom StellardR600: Rework subtarget info and remove AMDILDevice...
2013-06-07 Bill WendlingDon't cache the instruction and register info from...
2013-06-07 Tom StellardR600: Fix the fetch limits for R600 generation GPUs
2013-06-07 Tom StellardR600: Move Subtarget feature definitions into AMDGPU.td
2013-06-07 Tom StellardR600: Remove unnecessary include
2013-06-07 Benjamin KramerR600: Don't compare iterators of different maps.
2013-06-07 Benjamin KramerVincent says the element is at most once in the vector...
2013-06-07 Benjamin KramerR600: Fix a potential iterator invalidation issue.
2013-06-07 Vincent LejeuneR600: Remove an extra break in R600OptimizeVectorRegist...
2013-06-06 Vincent LejeuneR600: Rewrite an awkward loop in R600MachineScheduler
2013-06-06 Vincent LejeuneR600: Remove leftover code in R600MachineScheduler.cpp
2013-06-06 Bill WendlingCast to the correct type. Pointer, not reference.
2013-06-06 NAKAMURA TakumiR600OptimizeVectorRegisters.cpp: Tweak a warning. ...
2013-06-06 NAKAMURA TakumiR600OptimizeVectorRegisters.cpp: Suppress a warning...
2013-06-06 NAKAMURA TakumiTrailing linefeed.
2013-06-06 Bill WendlingCast to the proper type.
2013-06-05 Tom StellardR600: Replace predicate loop with predicate function
2013-06-05 Vincent LejeuneR600: Add a pass that merge Vector Register
2013-06-05 Vincent LejeuneR600: Schedule copy from phys register at beginning...
2013-06-05 Tom StellardR600: Make sure to schedule AR register uses and defs...
2013-06-05 Rafael EspindolaRevert "R600: Add a pass that merge Vector Register"
2013-06-04 Vincent LejeuneR600: Add a pass that merge Vector Register
2013-06-04 Vincent LejeuneR600: Const/Neg/Abs can be folded to dot4
2013-06-04 Vincent LejeuneR600: Swizzle texture/export instructions
2013-06-04 Aaron BallmanSilencing an MSVC warning about mixing bool and unsigne...
2013-06-03 Tom StellardR600/SI: Add support for work item and work group intri...
2013-06-03 Tom StellardR600/SI: Add a calling convention for compute shaders
2013-06-03 Tom StellardR600/SI: Custom lower i64 sign_extend
2013-06-03 Tom StellardR600/SI: Adjust some instructions' out register class...
2013-06-03 Tom StellardR600/SI: Handle REG_SEQUENCE in fitsRegClass()
2013-06-03 Tom StellardR600/SI: Handle nodes with glue results correctly SITar...
2013-06-03 Tom StellardR600/SI: Fixup CopyToReg register class in PostprocessI...
2013-06-03 Tom StellardR600/SI: Add support for global loads
2013-06-03 Tom StellardR600/SI: Rework MUBUF store instructions
2013-06-03 Vincent LejeuneR600: 3 op instructions have no write bit but the resul...
2013-06-03 Vincent LejeuneR600: CALL_FS consumes a stack size entry
2013-06-03 Vincent LejeuneR600: use capital letter for PV channel
2013-06-03 Vincent LejeuneR600: Constraints input regs of interp_xy,_zw
2013-05-31 Ahmed BougachaMake SubRegIndex size mandatory, following r183020.
2013-05-29 Patrik HagglundTemporary fix to get rid of gcc warning.
2013-05-25 Andrew TrickTrack IR ordering of SelectionDAG nodes 2/4.
2013-05-23 Tom StellardR600: Fix R600ControlFlowFinalizer not considering...
2013-05-23 Benjamin KramerMove passes from namespace llvm into anonymous namespac...
2013-05-23 Benjamin KramerR600: Hide symbols of implementation details.
2013-05-23 Aaron BallmanSetting the default value (fixes CRT assertions about...
2013-05-23 Rafael EspindolaFix 32 bit build in c++11 mode.
2013-05-23 Rafael EspindolaFix a leak on the r600 backend.
2013-05-23 Rafael Espindolaclang-format this file.
2013-05-22 Rafael EspindolaFix use after free (pr16103).
2013-05-22 Rafael EspindolaCheck that a function starts with llvm. before using...
2013-05-22 NAKAMURA TakumiR600ISelLowering.cpp: Avoid "using namespace Intrinsic...
2013-05-22 NAKAMURA TakumiR600: Whitespace and untabify.
2013-05-22 Owen AndersonCreate an FPOW SDNode opcode def in the target independ...
2013-05-22 Rafael EspindolaAttempt to fix the mingw32 bot.
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