R600: Const/Neg/Abs can be folded to dot4
[oota-llvm.git] / lib / Target / R600 /
2013-06-04 Vincent LejeuneR600: Const/Neg/Abs can be folded to dot4
2013-06-04 Vincent LejeuneR600: Swizzle texture/export instructions
2013-06-04 Aaron BallmanSilencing an MSVC warning about mixing bool and unsigne...
2013-06-03 Tom StellardR600/SI: Add support for work item and work group intri...
2013-06-03 Tom StellardR600/SI: Add a calling convention for compute shaders
2013-06-03 Tom StellardR600/SI: Custom lower i64 sign_extend
2013-06-03 Tom StellardR600/SI: Adjust some instructions' out register class...
2013-06-03 Tom StellardR600/SI: Handle REG_SEQUENCE in fitsRegClass()
2013-06-03 Tom StellardR600/SI: Handle nodes with glue results correctly SITar...
2013-06-03 Tom StellardR600/SI: Fixup CopyToReg register class in PostprocessI...
2013-06-03 Tom StellardR600/SI: Add support for global loads
2013-06-03 Tom StellardR600/SI: Rework MUBUF store instructions
2013-06-03 Vincent LejeuneR600: 3 op instructions have no write bit but the resul...
2013-06-03 Vincent LejeuneR600: CALL_FS consumes a stack size entry
2013-06-03 Vincent LejeuneR600: use capital letter for PV channel
2013-06-03 Vincent LejeuneR600: Constraints input regs of interp_xy,_zw
2013-05-31 Ahmed BougachaMake SubRegIndex size mandatory, following r183020.
2013-05-29 Patrik HagglundTemporary fix to get rid of gcc warning.
2013-05-25 Andrew TrickTrack IR ordering of SelectionDAG nodes 2/4.
2013-05-23 Tom StellardR600: Fix R600ControlFlowFinalizer not considering...
2013-05-23 Benjamin KramerMove passes from namespace llvm into anonymous namespac...
2013-05-23 Benjamin KramerR600: Hide symbols of implementation details.
2013-05-23 Aaron BallmanSetting the default value (fixes CRT assertions about...
2013-05-23 Rafael EspindolaFix 32 bit build in c++11 mode.
2013-05-23 Rafael EspindolaFix a leak on the r600 backend.
2013-05-23 Rafael Espindolaclang-format this file.
2013-05-22 Rafael EspindolaFix use after free (pr16103).
2013-05-22 Rafael EspindolaCheck that a function starts with llvm. before using...
2013-05-22 NAKAMURA TakumiR600ISelLowering.cpp: Avoid "using namespace Intrinsic...
2013-05-22 NAKAMURA TakumiR600: Whitespace and untabify.
2013-05-22 Owen AndersonCreate an FPOW SDNode opcode def in the target independ...
2013-05-22 Rafael EspindolaAttempt to fix the mingw32 bot.
2013-05-22 Rafael Espindolas/u_int32_t/uint32_t/
2013-05-22 Rafael EspindolaFix warning in non-assert build.
2013-05-20 Benjamin KramerR600: Fix bug detected by GCC warning.
2013-05-20 Tom StellardR600/SI: Use a multiclass for MUBUF_Load_Helper
2013-05-20 Tom StellardR600/SI: Add a pattern for S_LOAD_DWORDX2_* instructions
2013-05-20 Tom StellardR600/SI: Add pattern for rotr
2013-05-20 Tom StellardR600: Swap the legality of rotl and rotr
2013-05-20 Tom StellardR600/SI: Add patterns for 64-bit shift operations
2013-05-20 Tom StellardR600/SI: Use the same names for VOP3 operands and encod...
2013-05-20 Tom StellardR600/SI: Make fitsRegClass() operands const
2013-05-18 Matt ArsenaultAdd LLVMContext argument to getSetCCResultType
2013-05-17 Rafael EspindolaFix the build in c++11 mode.
2013-05-17 Vincent LejeuneR600: Lower int_load_input to copyFromReg instead of...
2013-05-17 Vincent LejeuneR600: Use bottom up scheduling algorithm
2013-05-17 Vincent LejeuneR600: Use depth first scheduling algorithm
2013-05-17 Vincent LejeuneR600: Replace big texture opcode switch in scheduler...
2013-05-17 Vincent LejeuneR600: Relax some vector constraints on Dot4.
2013-05-17 Vincent LejeuneR600: Improve texture handling
2013-05-17 Vincent LejeuneR600: Rename 128 bit registers.
2013-05-17 Vincent LejeuneR600: Some factorization
2013-05-17 Vincent LejeuneR600: Factorize Fetch size limit inside AMDGPUSubTarget
2013-05-17 Vincent LejeuneR600: prettier dump of clamp
2013-05-17 Tom StellardR600: Fix encoding for R600 family GPUs
2013-05-17 Tom StellardR600: Pass MCSubtargetInfo reference to R600CodeEmitter
2013-05-17 Christian KonigR600/SI: return undef instead of null for skipped arguments
2013-05-14 Tom StellardR600/SI: Add processor type for Hainan asic
2013-05-13 Rafael EspindolaRemove unused fields and arguments.
2013-05-13 Rafael EspindolaRemove the MachineMove class.
2013-05-10 Rafael EspindolaFix the R600 build.
2013-05-10 Tom StellardR600: Remove AMDILPeeopholeOptimizer and replace optimi...
2013-05-10 Tom StellardR600: Expand SUB for v2i32/v4i32
2013-05-10 Tom StellardR600: Expand MUL for v4i32/v2i32
2013-05-10 Tom StellardR600: Expand SRA for v4i32/v2i32
2013-05-10 Tom StellardR600: Expand vselect for v4i32 and v2i32
2013-05-06 Tom StellardR600/SI: Add intrinsic for MIMG IMAGE_GET_RESINFO opcode
2013-05-06 Tom StellardR600/SI: Handle arbitrary destination type in SITargetL...
2013-05-06 Tom StellardR600/SI: Add intrinsic for texture image loading
2013-05-06 Tom StellardR600/SI: Add pattern for uint_to_fp
2013-05-06 Tom StellardR600/SI: Add patterns for integer maxima / minima
2013-05-06 Tom StellardR600/SI: Add pattern for AMDGPU.trunc intrinsic
2013-05-06 Tom StellardR600: Remove dead code from the CodeEmitter v2
2013-05-06 Tom StellardR600: Emit config values in register / value pairs
2013-05-06 Tom StellardR600: Stop emitting the instruction type byte before...
2013-05-06 Tom StellardR600: Emit ISA for CALL_FS_* instructions
2013-05-03 Tom StellardR600: Expand vector or, shl, srl, and xor nodes
2013-05-03 Tom StellardR600: BFI_INT is a vector-only instruction
2013-05-03 Tom StellardR600: Add pattern for SHA-256 Ma function
2013-05-03 Tom StellardR600: Clean up comments in Processors.td
2013-05-02 Vincent LejeuneR600: Signed literals are 64bits wide
2013-05-02 Vincent LejeuneR600: If previous bundle is dot4, PV valid chan is...
2013-05-02 Vincent LejeuneR600: Improve asmPrint of ALU clause
2013-05-02 Vincent LejeuneR600: Prettier asmPrint of Alu
2013-05-02 Tom StellardR600: Use new tablegen syntax for patterns
2013-05-02 Tom StellardR600/SI: remove nonsense select pattern
2013-04-30 Vincent LejeuneR600: Always use texture cache for compute shaders
2013-04-30 Vincent LejeuneR600: use native for alu
2013-04-30 Vincent LejeuneR600: Packetize instructions
2013-04-30 Vincent LejeuneR600: Rework Scheduling to handle difference between...
2013-04-30 Vincent LejeuneR600: Add a Bank Swizzle operand
2013-04-30 Vincent LejeuneR600: Take inner dependency into tex/vtx clauses
2013-04-30 Vincent LejeuneR600: Turn TEX/VTX into native instructions
2013-04-30 Vincent LejeuneR600: Add FetchInst bit to instruction defs to denote...
2013-04-30 Vincent LejeuneR600: Add some new processor variants
2013-04-30 Vincent LejeuneR600: Clean up instruction class definitions
2013-04-30 Vincent LejeuneR600: config section now reports use of killgt
2013-04-29 Tom StellardR600: Use correct CF_END instruction on Northern Island...
2013-04-29 Tom StellardR600: Fix encoding of CF_END_{EG, R600} instructions
2013-04-26 Tom StellardR600: Initialize AMDGPUMachineFunction::ShaderType...
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