Remove Path::hasMagicNumber.
[oota-llvm.git] / lib / Target /
2013-06-12 Ulrich Weigand[MC/DWARF] Support .debug_frame / .debug_line code...
2013-06-12 Patrik HagglundFix gcc -flto build, by adding LLVM_ATTRIBUTE_USED to
2013-06-11 Eric ChristopherCorrect the def registers for the 8bit x86 divide instr...
2013-06-11 Eric ChristopherUse the Copy we defined above here.
2013-06-11 Akira HatanakaFix CMakeLists.
2013-06-11 Akira Hatanaka[mips] Add an IR transformation pass that optimizes...
2013-06-11 JF BastienARM FastISel fix sext/zext fold
2013-06-11 Akira Hatanaka[mips] Use function TargetInstrInfo::getRegClass.
2013-06-11 Benjamin KramerR600: Make helper functions static.
2013-06-11 NAKAMURA TakumiRework r183728, suppress assert(0) for now. Its behavio...
2013-06-11 Mihai PopaIt adds support for negative zero offsets for loads...
2013-06-11 Mihai PopaThis patch adds support for FPINST/FPINST2 as operands...
2013-06-11 Amaury de la VieuvilleARM: Enforce decoding rules for VLDn instructions
2013-06-11 Amaury de la VieuvilleARM: Fix STREX/LDREX reecoding
2013-06-11 NAKAMURA TakumiTweak a couple of tests on win32 hosts with +Asserts.
2013-06-11 NAKAMURA TakumiARMAsmBackend.cpp: Use Triple::isOSBinFormatCOFF()...
2013-06-11 NAKAMURA TakumiWhitespace.
2013-06-10 Tim NorthoverARM: diagnose ARM/Thumb assembly switches on CPUs only...
2013-06-10 Tim NorthoverX86: Stop LEA64_32r doing unspeakable things to its...
2013-06-10 Ulrich Weigand[PowerPC] Support extended sc mnemonic
2013-06-10 Ulrich Weigand[PowerPC] Support branch mnemonics with implied CR0
2013-06-10 Ulrich Weigand[PowerPC] Use multiclass to generate extended branch...
2013-06-10 Aaron BallmanSilencing an MSVC warning about comparing signed and...
2013-06-10 Amaury de la VieuvilleFix misleading comments in ARMAsmParser
2013-06-10 Amaury de la VieuvilleARM: ISB cannot be passed the same options as DMB
2013-06-10 Justin Holewinski[NVPTX] Remove old CONST_NOT_GEN address space that...
2013-06-09 Reed KotlerFix a regression I introduced when I expanded the compl...
2013-06-09 Logan ChienFix ARM unwind opcode assembler in several cases.
2013-06-09 Elena DemikhovskyRemoved PackedDouble domain from scalar instructions...
2013-06-09 JF BastienARM FastISel fix load register classes
2013-06-08 Venkatraman Govind... [Sparc] Delete FPMover Pass and remove Fp* Pseudo-instr...
2013-06-08 Amaury de la VieuvilleARM: fix VMOVvnf32 decoding when ambiguous with VCVT
2013-06-08 Amaury de la VieuvilleARM: enforce SRS decoding constraints
2013-06-08 Amaury de la VieuvilleARM: fix CPS decoding when ambiguous with QADD
2013-06-08 Amaury de la VieuvilleARM: fix VCVT decoding
2013-06-08 JF BastienFix unused variable warning from my previous patch.
2013-06-08 Akira Hatanaka[mips] Use a helper function which compares the size...
2013-06-07 Vincent LejeuneR600: Use a refined heuristic to choose when switching...
2013-06-07 Vincent LejeuneR600: Anti dep better handled in tex clause
2013-06-07 Jakob Stoklund OlesenRemember the anyext patterns.
2013-06-07 Jakob Stoklund OlesenAdd missing zextloadi1 to i64 patterns. PR16721.
2013-06-07 Hal FinkelDisallow i64 div/rem in PPC32 counter loops
2013-06-07 Bill WendlingDon't cache the instruction and register info from...
2013-06-07 Bill WendlingDon't cache the instruction and register info from...
2013-06-07 Bill WendlingRemove unused c'tor.
2013-06-07 Tom StellardR600: Fix calculation of stack offset in AMDGPUFrameLow...
2013-06-07 Bill WendlingDon't cache the instruction and register info from...
2013-06-07 Tom StellardR600: Rework subtarget info and remove AMDILDevice...
2013-06-07 Bill WendlingDon't cache the instruction and register info from...
2013-06-07 Bill WendlingDon't cache the instruction and register info from...
2013-06-07 Tom StellardR600: Fix the fetch limits for R600 generation GPUs
2013-06-07 Tom StellardR600: Move Subtarget feature definitions into AMDGPU.td
2013-06-07 Tom StellardR600: Remove unnecessary include
2013-06-07 JF BastienARM FastISel integer sext/zext improvements
2013-06-07 Benjamin KramerR600: Don't compare iterators of different maps.
2013-06-07 Benjamin KramerVincent says the element is at most once in the vector...
2013-06-07 Roman DivackyFix a typo in asm string of BP* family of instructions...
2013-06-07 Benjamin KramerR600: Fix a potential iterator invalidation issue.
2013-06-07 Vincent LejeuneR600: Remove an extra break in R600OptimizeVectorRegist...
2013-06-07 Benjamin KramerFold variable that's only used in assert into the assert.
2013-06-07 Bill WendlingDon't cache the instruction and register info from...
2013-06-07 Bill WendlingDon't cache the instruction and register info from...
2013-06-07 Bill WendlingDon't cache the instruction and register info from...
2013-06-07 Bill WendlingDon't cache the instruction and register info from...
2013-06-07 Bill WendlingDon't cache the instruction and register info from...
2013-06-07 Bill WendlingDon't cache the instruction and register info from...
2013-06-07 Bill WendlingDon't cache the instruction info and register info...
2013-06-07 Arnold SchwaighoferARM sched model: Use the right resources for DIV
2013-06-07 Arnold SchwaighoferARM sched model: Add VFP div instruction on Swift
2013-06-07 Arnold SchwaighoferARM sched model: Add SIMD/VFP load/store instructions...
2013-06-07 Venkatraman Govind... [Sparc]: Use cmp instruction instead of subcc to compar...
2013-06-06 Vincent LejeuneR600: Rewrite an awkward loop in R600MachineScheduler
2013-06-06 Arnold SchwaighoferRevert "ARM sched model: Add SIMD/VFP load/store instru...
2013-06-06 Arnold SchwaighoferARM sched model: Add SIMD/VFP load/store instructions...
2013-06-06 Arnold SchwaighoferARM sched model: Add integer VFP/SIMD instructions...
2013-06-06 Arnold SchwaighoferARM sched model: Add integer load/store instructions...
2013-06-06 Arnold SchwaighoferARM sched model: Add integer arithmetic instructions...
2013-06-06 Arnold SchwaighoferARM sched model: Cortex A9 - More InstRW sched resources
2013-06-06 Arnold SchwaighoferARM sched model: Add branch thumb instructions
2013-06-06 Arnold SchwaighoferARM sched model: Add branch thumb2 instructions
2013-06-06 Arnold SchwaighoferARM sched model: Add branch instructions
2013-06-06 Arnold SchwaighoferARM sched model: Add preload thumb2 instructions
2013-06-06 Arnold SchwaighoferARM sched model: Add preload instructions
2013-06-06 Arnold SchwaighoferARM sched model: Add more ALU and CMP thumb instructions
2013-06-06 Arnold SchwaighoferARM sched model: Add more ALU and CMP thumb2 instructions
2013-06-06 Vincent LejeuneR600: Remove leftover code in R600MachineScheduler.cpp
2013-06-06 Bill WendlingCast to the correct type. Pointer, not reference.
2013-06-06 NAKAMURA TakumiR600OptimizeVectorRegisters.cpp: Tweak a warning. ...
2013-06-06 NAKAMURA TakumiR600OptimizeVectorRegisters.cpp: Suppress a warning...
2013-06-06 NAKAMURA TakumiTrailing linefeed.
2013-06-06 Bill WendlingCast to the proper type.
2013-06-06 Bill WendlingCache the TargetLowering info object as a pointer.
2013-06-05 Tom StellardR600: Replace predicate loop with predicate function
2013-06-05 Vincent LejeuneR600: Add a pass that merge Vector Register
2013-06-05 Vincent LejeuneR600: Schedule copy from phys register at beginning...
2013-06-05 Akira Hatanaka[mips] brcond + setgt/setugt instruction selection...
2013-06-05 Michael Liao[PATCH] Fix VGATHER* operand constraints
2013-06-05 Arnold SchwaighoferARM sched model: Add more ALU and CMP instructions
2013-06-05 Arnold SchwaighoferARM sched model: Add divsion, loads, branches, vfp cvt
2013-06-05 Arnold SchwaighoferARMInstrInfo: Improve isSwiftFastImmShift
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