2013-06-05 |
Vincent Lejeune | R600: Add a pass that merge Vector Register |
tree | commitdiff |
2013-06-05 |
Vincent Lejeune | R600: Schedule copy from phys register at beginning... |
tree | commitdiff |
2013-06-05 |
Akira Hatanaka | [mips] brcond + setgt/setugt instruction selection... |
tree | commitdiff |
2013-06-05 |
Michael Liao | [PATCH] Fix VGATHER* operand constraints |
tree | commitdiff |
2013-06-05 |
Arnold Schwaighofer | ARM sched model: Add more ALU and CMP instructions |
tree | commitdiff |
2013-06-05 |
Arnold Schwaighofer | ARM sched model: Add divsion, loads, branches, vfp cvt |
tree | commitdiff |
2013-06-05 |
Arnold Schwaighofer | ARMInstrInfo: Improve isSwiftFastImmShift |
tree | commitdiff |
2013-06-05 |
Mihai Popa | This is a simple patch that changes RRX and RRXS to... |
tree | commitdiff |
2013-06-05 |
Tom Stellard | R600: Make sure to schedule AR register uses and defs... |
tree | commitdiff |
2013-06-05 |
Rafael Espindola | Revert "R600: Add a pass that merge Vector Register" |
tree | commitdiff |
2013-06-05 |
Rafael Espindola | Handle relocations that don't point to symbols. |
tree | commitdiff |
2013-06-04 |
Vincent Lejeune | R600: Add a pass that merge Vector Register |
tree | commitdiff |
2013-06-04 |
Vincent Lejeune | R600: Const/Neg/Abs can be folded to dot4 |
tree | commitdiff |
2013-06-04 |
Evan Cheng | Cortex-R5 can issue Thumb2 integer division instructions. |
tree | commitdiff |
2013-06-04 |
Arnold Schwaighofer | Revert series of sched model patches until I figure... |
tree | commitdiff |
2013-06-04 |
Arnold Schwaighofer | ARM sched model: Add VFP div instruction on Swift |
tree | commitdiff |
2013-06-04 |
Arnold Schwaighofer | ARM sched model: Add SIMD/VFP load/store instructions... |
tree | commitdiff |
2013-06-04 |
Arnold Schwaighofer | ARM sched model: Add integer VFP/SIMD instructions... |
tree | commitdiff |
2013-06-04 |
Arnold Schwaighofer | ARM sched model: Add integer load/store instructions... |
tree | commitdiff |
2013-06-04 |
Arnold Schwaighofer | ARM sched model: Add integer arithmetic instructions... |
tree | commitdiff |
2013-06-04 |
Arnold Schwaighofer | ARM sched model: Cortex A9 - More InstRW sched resources |
tree | commitdiff |
2013-06-04 |
Arnold Schwaighofer | ARM sched model: Add branch thumb instructions |
tree | commitdiff |
2013-06-04 |
Arnold Schwaighofer | ARM sched model: Add branch thumb2 instructions |
tree | commitdiff |
2013-06-04 |
Arnold Schwaighofer | ARM sched model: Add branch instructions |
tree | commitdiff |
2013-06-04 |
Arnold Schwaighofer | ARM sched model: Add preload thumb2 instructions |
tree | commitdiff |
2013-06-04 |
Arnold Schwaighofer | ARM sched model: Add preload instructions |
tree | commitdiff |
2013-06-04 |
Arnold Schwaighofer | ARM sched model: Add more ALU and CMP thumb instructions |
tree | commitdiff |
2013-06-04 |
Arnold Schwaighofer | ARM sched model: Add more ALU and CMP thumb2 instructions |
tree | commitdiff |
2013-06-04 |
Arnold Schwaighofer | ARM sched model: Add more ALU and CMP instructions |
tree | commitdiff |
2013-06-04 |
Arnold Schwaighofer | ARM sched model: Add divsion, loads, branches, vfp cvt |
tree | commitdiff |
2013-06-04 |
Arnold Schwaighofer | ARMInstrInfo: Improve isSwiftFastImmShift |
tree | commitdiff |
2013-06-04 |
Venkatraman Govind... | Sparc: No functionality change. Cleanup whitespaces... |
tree | commitdiff |
2013-06-04 |
David Majnemer | ARM: Fix crash in ARM backend inside of ARMConstantIsla... |
tree | commitdiff |
2013-06-04 |
Vincent Lejeune | R600: Swizzle texture/export instructions |
tree | commitdiff |
2013-06-04 |
Vladimir Medic | Test commit for user vmedic, to verify commit access... |
tree | commitdiff |
2013-06-04 |
Aaron Ballman | Silencing an MSVC warning about mixing bool and unsigne... |
tree | commitdiff |
2013-06-03 |
Tom Stellard | R600/SI: Add support for work item and work group intri... |
tree | commitdiff |
2013-06-03 |
Tom Stellard | R600/SI: Add a calling convention for compute shaders |
tree | commitdiff |
2013-06-03 |
Tom Stellard | R600/SI: Custom lower i64 sign_extend |
tree | commitdiff |
2013-06-03 |
Tom Stellard | R600/SI: Adjust some instructions' out register class... |
tree | commitdiff |
2013-06-03 |
Tom Stellard | R600/SI: Handle REG_SEQUENCE in fitsRegClass() |
tree | commitdiff |
2013-06-03 |
Tom Stellard | R600/SI: Handle nodes with glue results correctly SITar... |
tree | commitdiff |
2013-06-03 |
Tom Stellard | R600/SI: Fixup CopyToReg register class in PostprocessI... |
tree | commitdiff |
2013-06-03 |
Tom Stellard | R600/SI: Add support for global loads |
tree | commitdiff |
2013-06-03 |
Tom Stellard | R600/SI: Rework MUBUF store instructions |
tree | commitdiff |
2013-06-03 |
Vincent Lejeune | R600: 3 op instructions have no write bit but the resul... |
tree | commitdiff |
2013-06-03 |
Vincent Lejeune | R600: CALL_FS consumes a stack size entry |
tree | commitdiff |
2013-06-03 |
Vincent Lejeune | R600: use capital letter for PV channel |
tree | commitdiff |
2013-06-03 |
Vincent Lejeune | R600: Constraints input regs of interp_xy,_zw |
tree | commitdiff |
2013-06-03 |
Ahmed Bougacha | X86: sub_xmm registers are 128 bits wide. |
tree | commitdiff |
2013-06-03 |
Venkatraman Govind... | Sparc: Add support for indirect branch and blockaddress... |
tree | commitdiff |
2013-06-03 |
Venkatraman Govind... | Sparc: When storing 0, use %g0 directly in the store... |
tree | commitdiff |
2013-06-02 |
Venkatraman Govind... | Sparc: Combine add/or/sethi instruction with restore... |
tree | commitdiff |
2013-06-02 |
Venkatraman Govind... | Sparc: Perform leaf procedure optimization by default |
tree | commitdiff |
2013-06-01 |
Venkatraman Govind... | Sparc: Mark functions calling llvm.vastart and llvm... |
tree | commitdiff |
2013-06-01 |
Tim Northover | Revert r183069: "TMP: LEA64_32r fixing" |
tree | commitdiff |
2013-06-01 |
Tim Northover | TMP: LEA64_32r fixing |
tree | commitdiff |
2013-06-01 |
Tim Northover | X86: change MOV64ri64i32 into MOV32ri64 |
tree | commitdiff |
2013-06-01 |
Venkatraman Govind... | [Sparc] Generate correct code for leaf functions with... |
tree | commitdiff |
2013-05-31 |
Ahmed Bougacha | Make SubRegIndex size mandatory, following r183020. |
tree | commitdiff |
2013-05-31 |
Eric Christopher | Temporarily Revert "X86: change MOV64ri64i32 into MOV32... |
tree | commitdiff |
2013-05-31 |
Benjamin Kramer | NVPTX: Don't even create a regalloc if we're not going... |
tree | commitdiff |
2013-05-31 |
Ahmed Bougacha | Add a way to define the bit range covered by a SubRegIndex. |
tree | commitdiff |
2013-05-31 |
Tim Northover | ARM: permit upper-case BE/LE on setend instruction |
tree | commitdiff |
2013-05-31 |
Tim Northover | ARM: add fstmx and fldmx instructions for assembly |
tree | commitdiff |
2013-05-31 |
Tim Northover | ARM: fix VEXT encoding corner case |
tree | commitdiff |
2013-05-31 |
Richard Sandiford | [SystemZ] Don't use LOAD and STORE REVERSED for volatil... |
tree | commitdiff |
2013-05-31 |
Justin Holewinski | [NVPTX] Re-enable support for virtual registers in... |
tree | commitdiff |
2013-05-31 |
Tim Northover | X86: change MOV64ri64i32 into MOV32ri64 |
tree | commitdiff |
2013-05-31 |
Akira Hatanaka | [mips] Big-endian code generation for atomic instructions. |
tree | commitdiff |
2013-05-30 |
Rafael Espindola | Revert r182937 and r182877. |
tree | commitdiff |
2013-05-30 |
Tim Northover | X86: use sub-register sequences for MOV*r0 operations |
tree | commitdiff |
2013-05-30 |
Justin Holewinski | [NVPTX] Fix case where a sext load of an i1 type may... |
tree | commitdiff |
2013-05-30 |
Tim Northover | X86: change zext moves to use sub-register infrastructure. |
tree | commitdiff |
2013-05-30 |
Richard Sandiford | [SystemZ] Enable unaligned accesses |
tree | commitdiff |
2013-05-29 |
Andrew Trick | Order CALLSEQ_START and CALLSEQ_END nodes. |
tree | commitdiff |
2013-05-29 |
Ahmed Bougacha | X86: Fix Defs/Uses for insts that imp-def/imp-use both... |
tree | commitdiff |
2013-05-29 |
Chad Rosier | Don't assume the registers will be enumerated sequentially. |
tree | commitdiff |
2013-05-29 |
JF Bastien | Enable FastISel on ARM for Linux and NaCl |
tree | commitdiff |
2013-05-29 |
Bill Wendling | Don't reach into the middle of TargetMachine and cache... |
tree | commitdiff |
2013-05-29 |
JF Bastien | Tidy some register classes for ARM and Thumb |
tree | commitdiff |
2013-05-29 |
NAKAMURA Takumi | SparcFrameLowering.cpp: Mark verifyLeafProcRegUse(... |
tree | commitdiff |
2013-05-29 |
Richard Sandiford | [SystemZ] Immediate compare-and-branch support |
tree | commitdiff |
2013-05-29 |
Patrik Hagglund | Temporary fix to get rid of gcc warning. |
tree | commitdiff |
2013-05-29 |
Venkatraman Govind... | [Sparc] Add support for leaf functions in sparc backend. |
tree | commitdiff |
2013-05-28 |
Jack Carter | Mips assembler: Improve set register alias handling |
tree | commitdiff |
2013-05-28 |
Tim Northover | AArch64: clarify -help message |
tree | commitdiff |
2013-05-28 |
Jyotsna Verma | Hexagon: Typo fix. |
tree | commitdiff |
2013-05-28 |
Richard Sandiford | [SystemZ] Register compare-and-branch support |
tree | commitdiff |
2013-05-28 |
Richard Sandiford | [SystemZ] Tweak SystemZInstrInfo::isBranch() interface |
tree | commitdiff |
2013-05-27 |
Rafael Espindola | Make helper functions static. |
tree | commitdiff |
2013-05-27 |
Preston Gurd | Convert sqrt functions into sqrt instructions when... |
tree | commitdiff |
2013-05-27 |
Hal Finkel | PPC: Add a isConsecutiveLS utility function |
tree | commitdiff |
2013-05-26 |
Hal Finkel | Prefer to duplicate PPC Altivec loads when expanding... |
tree | commitdiff |
2013-05-25 |
Hal Finkel | PPC: Combine duplicate (offset) lvsl Altivec intrinsics |
tree | commitdiff |
2013-05-25 |
Andrew Trick | Track IR ordering of SelectionDAG nodes 3/4. |
tree | commitdiff |
2013-05-25 |
Andrew Trick | Track IR ordering of SelectionDAG nodes 2/4. |
tree | commitdiff |
2013-05-24 |
Hal Finkel | PPC: Initial support for permutation-based unaligned... |
tree | commitdiff |
2013-05-24 |
Quentin Colombet | Follow up of the introduction of MCSymbolizer. |
tree | commitdiff |
2013-05-24 |
Michael J. Spencer | Replace Count{Leading,Trailing}Zeros_{32,64} with count... |
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