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Don't cache the instruction info and register info objects.
[oota-llvm.git] / lib / Target /
2013-06-07 Bill WendlingDon't cache the instruction info and register info... tree | commitdiff
2013-06-07 Arnold SchwaighoferARM sched model: Use the right resources for DIV tree | commitdiff
2013-06-07 Arnold SchwaighoferARM sched model: Add VFP div instruction on Swift tree | commitdiff
2013-06-07 Arnold SchwaighoferARM sched model: Add SIMD/VFP load/store instructions... tree | commitdiff
2013-06-07 Venkatraman Govind... [Sparc]: Use cmp instruction instead of subcc to compar... tree | commitdiff
2013-06-06 Vincent LejeuneR600: Rewrite an awkward loop in R600MachineScheduler tree | commitdiff
2013-06-06 Arnold SchwaighoferRevert "ARM sched model: Add SIMD/VFP load/store instru... tree | commitdiff
2013-06-06 Arnold SchwaighoferARM sched model: Add SIMD/VFP load/store instructions... tree | commitdiff
2013-06-06 Arnold SchwaighoferARM sched model: Add integer VFP/SIMD instructions... tree | commitdiff
2013-06-06 Arnold SchwaighoferARM sched model: Add integer load/store instructions... tree | commitdiff
2013-06-06 Arnold SchwaighoferARM sched model: Add integer arithmetic instructions... tree | commitdiff
2013-06-06 Arnold SchwaighoferARM sched model: Cortex A9 - More InstRW sched resources tree | commitdiff
2013-06-06 Arnold SchwaighoferARM sched model: Add branch thumb instructions tree | commitdiff
2013-06-06 Arnold SchwaighoferARM sched model: Add branch thumb2 instructions tree | commitdiff
2013-06-06 Arnold SchwaighoferARM sched model: Add branch instructions tree | commitdiff
2013-06-06 Arnold SchwaighoferARM sched model: Add preload thumb2 instructions tree | commitdiff
2013-06-06 Arnold SchwaighoferARM sched model: Add preload instructions tree | commitdiff
2013-06-06 Arnold SchwaighoferARM sched model: Add more ALU and CMP thumb instructions tree | commitdiff
2013-06-06 Arnold SchwaighoferARM sched model: Add more ALU and CMP thumb2 instructions tree | commitdiff
2013-06-06 Vincent LejeuneR600: Remove leftover code in R600MachineScheduler.cpp tree | commitdiff
2013-06-06 Bill WendlingCast to the correct type. Pointer, not reference. tree | commitdiff
2013-06-06 NAKAMURA TakumiR600OptimizeVectorRegisters.cpp: Tweak a warning. ... tree | commitdiff
2013-06-06 NAKAMURA TakumiR600OptimizeVectorRegisters.cpp: Suppress a warning... tree | commitdiff
2013-06-06 NAKAMURA TakumiTrailing linefeed. tree | commitdiff
2013-06-06 Bill WendlingCast to the proper type. tree | commitdiff
2013-06-06 Bill WendlingCache the TargetLowering info object as a pointer. tree | commitdiff
2013-06-05 Tom StellardR600: Replace predicate loop with predicate function tree | commitdiff
2013-06-05 Vincent LejeuneR600: Add a pass that merge Vector Register tree | commitdiff
2013-06-05 Vincent LejeuneR600: Schedule copy from phys register at beginning... tree | commitdiff
2013-06-05 Akira Hatanaka[mips] brcond + setgt/setugt instruction selection... tree | commitdiff
2013-06-05 Michael Liao[PATCH] Fix VGATHER* operand constraints tree | commitdiff
2013-06-05 Arnold SchwaighoferARM sched model: Add more ALU and CMP instructions tree | commitdiff
2013-06-05 Arnold SchwaighoferARM sched model: Add divsion, loads, branches, vfp cvt tree | commitdiff
2013-06-05 Arnold SchwaighoferARMInstrInfo: Improve isSwiftFastImmShift tree | commitdiff
2013-06-05 Mihai PopaThis is a simple patch that changes RRX and RRXS to... tree | commitdiff
2013-06-05 Tom StellardR600: Make sure to schedule AR register uses and defs... tree | commitdiff
2013-06-05 Rafael EspindolaRevert "R600: Add a pass that merge Vector Register" tree | commitdiff
2013-06-05 Rafael EspindolaHandle relocations that don't point to symbols. tree | commitdiff
2013-06-04 Vincent LejeuneR600: Add a pass that merge Vector Register tree | commitdiff
2013-06-04 Vincent LejeuneR600: Const/Neg/Abs can be folded to dot4 tree | commitdiff
2013-06-04 Evan ChengCortex-R5 can issue Thumb2 integer division instructions. tree | commitdiff
2013-06-04 Arnold SchwaighoferRevert series of sched model patches until I figure... tree | commitdiff
2013-06-04 Arnold SchwaighoferARM sched model: Add VFP div instruction on Swift tree | commitdiff
2013-06-04 Arnold SchwaighoferARM sched model: Add SIMD/VFP load/store instructions... tree | commitdiff
2013-06-04 Arnold SchwaighoferARM sched model: Add integer VFP/SIMD instructions... tree | commitdiff
2013-06-04 Arnold SchwaighoferARM sched model: Add integer load/store instructions... tree | commitdiff
2013-06-04 Arnold SchwaighoferARM sched model: Add integer arithmetic instructions... tree | commitdiff
2013-06-04 Arnold SchwaighoferARM sched model: Cortex A9 - More InstRW sched resources tree | commitdiff
2013-06-04 Arnold SchwaighoferARM sched model: Add branch thumb instructions tree | commitdiff
2013-06-04 Arnold SchwaighoferARM sched model: Add branch thumb2 instructions tree | commitdiff
2013-06-04 Arnold SchwaighoferARM sched model: Add branch instructions tree | commitdiff
2013-06-04 Arnold SchwaighoferARM sched model: Add preload thumb2 instructions tree | commitdiff
2013-06-04 Arnold SchwaighoferARM sched model: Add preload instructions tree | commitdiff
2013-06-04 Arnold SchwaighoferARM sched model: Add more ALU and CMP thumb instructions tree | commitdiff
2013-06-04 Arnold Schwaighofer ARM sched model: Add more ALU and CMP thumb2 instructions tree | commitdiff
2013-06-04 Arnold SchwaighoferARM sched model: Add more ALU and CMP instructions tree | commitdiff
2013-06-04 Arnold SchwaighoferARM sched model: Add divsion, loads, branches, vfp cvt tree | commitdiff
2013-06-04 Arnold SchwaighoferARMInstrInfo: Improve isSwiftFastImmShift tree | commitdiff
2013-06-04 Venkatraman Govind... Sparc: No functionality change. Cleanup whitespaces... tree | commitdiff
2013-06-04 David MajnemerARM: Fix crash in ARM backend inside of ARMConstantIsla... tree | commitdiff
2013-06-04 Vincent LejeuneR600: Swizzle texture/export instructions tree | commitdiff
2013-06-04 Vladimir MedicTest commit for user vmedic, to verify commit access... tree | commitdiff
2013-06-04 Aaron BallmanSilencing an MSVC warning about mixing bool and unsigne... tree | commitdiff
2013-06-03 Tom StellardR600/SI: Add support for work item and work group intri... tree | commitdiff
2013-06-03 Tom StellardR600/SI: Add a calling convention for compute shaders tree | commitdiff
2013-06-03 Tom StellardR600/SI: Custom lower i64 sign_extend tree | commitdiff
2013-06-03 Tom StellardR600/SI: Adjust some instructions' out register class... tree | commitdiff
2013-06-03 Tom StellardR600/SI: Handle REG_SEQUENCE in fitsRegClass() tree | commitdiff
2013-06-03 Tom StellardR600/SI: Handle nodes with glue results correctly SITar... tree | commitdiff
2013-06-03 Tom StellardR600/SI: Fixup CopyToReg register class in PostprocessI... tree | commitdiff
2013-06-03 Tom StellardR600/SI: Add support for global loads tree | commitdiff
2013-06-03 Tom StellardR600/SI: Rework MUBUF store instructions tree | commitdiff
2013-06-03 Vincent LejeuneR600: 3 op instructions have no write bit but the resul... tree | commitdiff
2013-06-03 Vincent LejeuneR600: CALL_FS consumes a stack size entry tree | commitdiff
2013-06-03 Vincent LejeuneR600: use capital letter for PV channel tree | commitdiff
2013-06-03 Vincent LejeuneR600: Constraints input regs of interp_xy,_zw tree | commitdiff
2013-06-03 Ahmed BougachaX86: sub_xmm registers are 128 bits wide. tree | commitdiff
2013-06-03 Venkatraman Govind... Sparc: Add support for indirect branch and blockaddress... tree | commitdiff
2013-06-03 Venkatraman Govind... Sparc: When storing 0, use %g0 directly in the store... tree | commitdiff
2013-06-02 Venkatraman Govind... Sparc: Combine add/or/sethi instruction with restore... tree | commitdiff
2013-06-02 Venkatraman Govind... Sparc: Perform leaf procedure optimization by default tree | commitdiff
2013-06-01 Venkatraman Govind... Sparc: Mark functions calling llvm.vastart and llvm... tree | commitdiff
2013-06-01 Tim NorthoverRevert r183069: "TMP: LEA64_32r fixing" tree | commitdiff
2013-06-01 Tim NorthoverTMP: LEA64_32r fixing tree | commitdiff
2013-06-01 Tim NorthoverX86: change MOV64ri64i32 into MOV32ri64 tree | commitdiff
2013-06-01 Venkatraman Govind... [Sparc] Generate correct code for leaf functions with... tree | commitdiff
2013-05-31 Ahmed BougachaMake SubRegIndex size mandatory, following r183020. tree | commitdiff
2013-05-31 Eric ChristopherTemporarily Revert "X86: change MOV64ri64i32 into MOV32... tree | commitdiff
2013-05-31 Benjamin KramerNVPTX: Don't even create a regalloc if we're not going... tree | commitdiff
2013-05-31 Ahmed BougachaAdd a way to define the bit range covered by a SubRegIndex. tree | commitdiff
2013-05-31 Tim NorthoverARM: permit upper-case BE/LE on setend instruction tree | commitdiff
2013-05-31 Tim NorthoverARM: add fstmx and fldmx instructions for assembly tree | commitdiff
2013-05-31 Tim NorthoverARM: fix VEXT encoding corner case tree | commitdiff
2013-05-31 Richard Sandiford[SystemZ] Don't use LOAD and STORE REVERSED for volatil... tree | commitdiff
2013-05-31 Justin Holewinski[NVPTX] Re-enable support for virtual registers in... tree | commitdiff
2013-05-31 Tim NorthoverX86: change MOV64ri64i32 into MOV32ri64 tree | commitdiff
2013-05-31 Akira Hatanaka[mips] Big-endian code generation for atomic instructions. tree | commitdiff
2013-05-30 Rafael EspindolaRevert r182937 and r182877. tree | commitdiff
2013-05-30 Tim NorthoverX86: use sub-register sequences for MOV*r0 operations tree | commitdiff
2013-05-30 Justin Holewinski[NVPTX] Fix case where a sext load of an i1 type may... tree | commitdiff
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C/C++ LLVM-based compilers that forbids OOTA behaviors