2014-12-11 |
Matt Arsenault | R600/SI: Handle physical registers in getOpRegClass |
tree | commitdiff |
2014-12-11 |
Matt Arsenault | R600/SI: Don't verify constant bus usage of flag ops |
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2014-12-11 |
Sanjay Patel | return without temporary; NFC |
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2014-12-11 |
Matthias Braun | Enable MachineVerifier in debug mode for X86, ARM,... |
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2014-12-11 |
Ahmed Bougacha | [X86] Add a temporary testcase for PR21876/r223996. |
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2014-12-11 |
Hal Finkel | [PowerPC] Better lowering for add/or of a FrameIndex |
tree | commitdiff |
2014-12-11 |
Matt Arsenault | R600/SI: Use unordered equal instructions |
tree | commitdiff |
2014-12-11 |
Matt Arsenault | R600/SI: Make more unordered comparisons legal |
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2014-12-11 |
Matt Arsenault | R600/SI: Use unordered not equal instructions |
tree | commitdiff |
2014-12-11 |
Matthias Braun | [CodeGen] Add print and verify pass after each MachineF... |
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2014-12-11 |
Rafael Espindola | This reverts commit r224043 and r224042. |
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2014-12-11 |
Matthias Braun | Enable machineverifier in debug mode for X86, ARM,... |
tree | commitdiff |
2014-12-11 |
Matthias Braun | [CodeGen] Add print and verify pass after each MachineF... |
tree | commitdiff |
2014-12-11 |
Colin LeMahieu | [Hexagon] Renaming classes in preparation for replacement. |
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2014-12-11 |
Tim Northover | ARM: convert isTargetIOS checks to isTargetDarwin. |
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2014-12-11 |
Hal Finkel | [PowerPC] Implement BuildSDIVPow2, lower i64 pow2 sdiv... |
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2014-12-11 |
Cameron McInally | [AVX512] Add support for 512b variable bit shift intrin... |
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2014-12-11 |
Colin LeMahieu | [Hexagon] Ading i64 <- i32, i32 sextw pattern. |
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2014-12-11 |
Colin LeMahieu | [Hexagon] Adding encoding information for sign extend... |
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2014-12-11 |
Elena Demikhovsky | AVX-512: Added all forms of COMPRESS instruction |
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2014-12-11 |
Jozef Kolek | [mips][microMIPS] Implement CodeGen support for LI16... |
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2014-12-11 |
Michael Kuperstein | [X86] When converting movs to pushes, don't assume... |
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2014-12-11 |
Elena Demikhovsky | AVX-512: Fixed a bug in lowering setcc for MVT::i1... |
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2014-12-11 |
Kumar Sukhani | test commit (spelling correction) |
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2014-12-11 |
Ahmed Bougacha | [X86] Add back AVX2 VR256 PMOVX patterns. |
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2014-12-10 |
Tim Northover | ARM: correctly expand LDR-lit based globals. |
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2014-12-10 |
Colin LeMahieu | [Hexagon] Adding combine ri/ir instructions. |
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2014-12-10 |
Colin LeMahieu | [Hexagon] Adding encodings for JR class instructions... |
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2014-12-10 |
Juergen Ributzka | [AArch64] MachO large code-model: Materialize FP consta... |
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2014-12-10 |
Marek Olsak | R600/SI: Use getTargetConstant in AdjustRegClass |
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2014-12-10 |
Colin LeMahieu | [Hexagon] Adding JR class predicated call reg instructions. |
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2014-12-10 |
Sanjay Patel | Match new shuffle codegen for MOVHPD patterns |
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2014-12-10 |
Michael Kuperstein | [X86] Make a code path in EltsFromConsecutiveLoads... |
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2014-12-10 |
Ahmed Bougacha | [ARM] Combine base-updating/post-incrementing vector... |
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2014-12-09 |
Colin LeMahieu | [Hexagon] [NFC] Cleaning up unused classes. |
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2014-12-09 |
Ahmed Bougacha | [ARM] Factor out base-updating VLD/VST combiner functio... |
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2014-12-09 |
Ahmed Bougacha | [ARM] Move the store combiner function down. NFC. |
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2014-12-09 |
Ahmed Bougacha | [ARM] Also support v2f64 vld1/vst1. |
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2014-12-09 |
Colin LeMahieu | [Hexagon] Fixing broken tests. |
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2014-12-09 |
Colin LeMahieu | [Hexagon] Updating rr/ri 32/64 transfer encodings and... |
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2014-12-09 |
Juergen Ributzka | [FastISel][AArch64] Fix a missing nullptr check in... |
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2014-12-09 |
Colin LeMahieu | [Hexagon] Adding word combine dot-new form and replacin... |
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2014-12-09 |
Robert Khasanov | [AVX512] Added lowering for VBROADCASTSS/SD instructions. |
tree | commitdiff |
2014-12-09 |
Duncan P. N. Exon... | IR: Split Metadata from Value |
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2014-12-09 |
Colin LeMahieu | [Hexagon] Updating predicate register transfers and... |
tree | commitdiff |
2014-12-09 |
Bill Schmidt | [PowerPC 4/4] Enable little-endian support for VSX. |
tree | commitdiff |
2014-12-09 |
Bill Schmidt | [PowerPC 3/4] Little-endian adjustments for VSX vector... |
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2014-12-09 |
Bill Schmidt | [PowerPC 2/4] Little-endian adjustments for VSX insert... |
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2014-12-09 |
Robert Khasanov | [AVX512] Added VPBROADCAST{BWDQ} (Load with Broadcast... |
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2014-12-09 |
Bill Schmidt | [PowerPC 1/4] Little-endian adjustments for VSX loads... |
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2014-12-09 |
Chandler Carruth | [x86] Fix the test to actually test things for the... |
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2014-12-09 |
Aaron Ballman | Removing an unused variable to silence a -Wunused-but... |
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2014-12-09 |
Asiri Rathnayake | Fix modified immediate bug reported by MC Hammer. |
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2014-12-09 |
Chandler Carruth | [x86] Bring some sanity to the x86 CPU processor defini... |
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2014-12-09 |
Elena Demikhovsky | AVX-512: Added some comments to ERI scalar intrinsics. |
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2014-12-09 |
Mohit K. Bhakkad | test commit (spelling correction) |
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2014-12-09 |
Michael Kuperstein | [X86] Convert esp-relative movs of function arguments... |
tree | commitdiff |
2014-12-09 |
Bill Schmidt | Restore r223709 as it was meant to be, and enable Featu... |
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2014-12-09 |
NAKAMURA Takumi | Revert r223709, "[PowerPC]Activate FeatureVSX for the... |
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2014-12-09 |
Tom Stellard | R600/SI: Set MayStore = 0 on MUBUF loads |
tree | commitdiff |
2014-12-09 |
Tom Stellard | R600/SI: Move setting of the lds bit to the base MUBUF... |
tree | commitdiff |
2014-12-08 |
Colin LeMahieu | [Hexagon] Removing old def versions and replacing usage... |
tree | commitdiff |
2014-12-08 |
Colin LeMahieu | [Hexagon] Adding any8, all8, and/or/xor/andn/orn/not... |
tree | commitdiff |
2014-12-08 |
Bill Seurer | [PowerPC]Activate FeatureVSX for the Power target |
tree | commitdiff |
2014-12-08 |
Hal Finkel | [PowerPC] Don't use a non-allocatable register to imple... |
tree | commitdiff |
2014-12-08 |
Colin LeMahieu | [Hexagon] Adding xtype doubleword add, sub, and, or... |
tree | commitdiff |
2014-12-08 |
Colin LeMahieu | [Hexagon] Adding xtype doubleword comparisons. Removin... |
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2014-12-08 |
Colin LeMahieu | [Hexagon] Adding xtype parity, min, minu, max, maxu... |
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2014-12-08 |
Colin LeMahieu | [Hexagon] Adding xtype halfword add/sub ll/hl/lh/hh... |
tree | commitdiff |
2014-12-08 |
Matt Arsenault | R600/SI: Move continue after checking s_mov_b32. |
tree | commitdiff |
2014-12-08 |
Colin LeMahieu | [Hexagon] Adding add/sub with saturation. Removing... |
tree | commitdiff |
2014-12-08 |
Bruno Cardoso Lopes | [CompactUnwind] Fix register encoding logic |
tree | commitdiff |
2014-12-08 |
Tim Northover | AArch64: treat HFAs containing "half" types as blocks... |
tree | commitdiff |
2014-12-08 |
Andrea Di Biagio | [X86] Improved tablegen patters for matching TZCNT... |
tree | commitdiff |
2014-12-08 |
Colin LeMahieu | [Hexagon] Adding combine reg, reg with predicated forms. |
tree | commitdiff |
2014-12-08 |
Colin LeMahieu | [Hexagon] Adding packhl instruction. |
tree | commitdiff |
2014-12-08 |
Daniel Sanders | [mips] Add Mips-specific CCIf's for accessing the MipsC... |
tree | commitdiff |
2014-12-08 |
Andrea Di Biagio | [X86] Improved lowering of packed v8i16 vector shifts... |
tree | commitdiff |
2014-12-08 |
Elena Demikhovsky | X86 intrinsics moved form X86ISelLowering.cpp to X86Int... |
tree | commitdiff |
2014-12-07 |
Marek Olsak | R600/SI: Disable VMEM and SMEM clauses by breaking... |
tree | commitdiff |
2014-12-07 |
Marek Olsak | R600/SI: Set 20-bit immediate byte offset for SMRD... |
tree | commitdiff |
2014-12-07 |
Marek Olsak | R600/SI: Update instruction conversions for VI |
tree | commitdiff |
2014-12-07 |
Marek Olsak | R600/SI: Add VI instructions |
tree | commitdiff |
2014-12-07 |
Marek Olsak | R600/SI: Add SCC Defs/Uses to SOP1 and SOP2 opcodes |
tree | commitdiff |
2014-12-06 |
Benjamin Kramer | Make the DenseMap bucket type configurable and use... |
tree | commitdiff |
2014-12-06 |
Tom Stellard | R600/SI: Restore PrivateGlobalPrefix to the default... |
tree | commitdiff |
2014-12-06 |
Ahmed Bougacha | [X86] Refactor PMOV[SZ]Xrm to add missing AVX2 patterns. |
tree | commitdiff |
2014-12-06 |
Tim Northover | AArch64: use explicit MVT::i64 when creating EXTRACT_SU... |
tree | commitdiff |
2014-12-05 |
Ahmed Bougacha | [X86] Cleanup FCOPYSIGN lowering. NFC intended. |
tree | commitdiff |
2014-12-05 |
Colin LeMahieu | [Hexagon] Relocating logical instructions and templates... |
tree | commitdiff |
2014-12-05 |
Colin LeMahieu | [Hexagon] Adding sub/and/or reg, imm forms |
tree | commitdiff |
2014-12-05 |
Sanjay Patel | Optimize merging of scalar loads for 32-byte vectors... |
tree | commitdiff |
2014-12-05 |
Colin LeMahieu | [Hexagon] Updating mux_ir/ri/ii/rr with encoding bits |
tree | commitdiff |
2014-12-05 |
Jan Wen Voung | Use 32-bit ebp for NaCl64 in a limited case: llvm.frame... |
tree | commitdiff |
2014-12-05 |
Bill Seurer | [PowerPC]Add VSX loads/stores to fastisel for PPC target |
tree | commitdiff |
2014-12-05 |
Colin LeMahieu | [Hexagon] Adding tfrih/l instructions. |
tree | commitdiff |
2014-12-05 |
Andrea Di Biagio | [X86] Improved lowering of packed vector shifts to... |
tree | commitdiff |
2014-12-05 |
Colin LeMahieu | [Hexagon] Adding add reg, imm form with encoding bits... |
tree | commitdiff |
2014-12-05 |
Colin LeMahieu | [Hexagon] Adding DoubleRegs decoder. Moving C2_mux... |
tree | commitdiff |
2014-12-05 |
Colin LeMahieu | [Hexagon] [NFC] Rearranging patterns and mux instruction. |
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