R600/SI: Handle physical registers in getOpRegClass
[oota-llvm.git] / lib / Target /
2014-12-11 Matt ArsenaultR600/SI: Handle physical registers in getOpRegClass
2014-12-11 Matt ArsenaultR600/SI: Don't verify constant bus usage of flag ops
2014-12-11 Sanjay Patelreturn without temporary; NFC
2014-12-11 Matthias BraunEnable MachineVerifier in debug mode for X86, ARM,...
2014-12-11 Ahmed Bougacha[X86] Add a temporary testcase for PR21876/r223996.
2014-12-11 Hal Finkel[PowerPC] Better lowering for add/or of a FrameIndex
2014-12-11 Matt ArsenaultR600/SI: Use unordered equal instructions
2014-12-11 Matt ArsenaultR600/SI: Make more unordered comparisons legal
2014-12-11 Matt ArsenaultR600/SI: Use unordered not equal instructions
2014-12-11 Matthias Braun[CodeGen] Add print and verify pass after each MachineF...
2014-12-11 Rafael EspindolaThis reverts commit r224043 and r224042.
2014-12-11 Matthias BraunEnable machineverifier in debug mode for X86, ARM,...
2014-12-11 Matthias Braun[CodeGen] Add print and verify pass after each MachineF...
2014-12-11 Colin LeMahieu[Hexagon] Renaming classes in preparation for replacement.
2014-12-11 Tim NorthoverARM: convert isTargetIOS checks to isTargetDarwin.
2014-12-11 Hal Finkel[PowerPC] Implement BuildSDIVPow2, lower i64 pow2 sdiv...
2014-12-11 Cameron McInally[AVX512] Add support for 512b variable bit shift intrin...
2014-12-11 Colin LeMahieu[Hexagon] Ading i64 <- i32, i32 sextw pattern.
2014-12-11 Colin LeMahieu[Hexagon] Adding encoding information for sign extend...
2014-12-11 Elena DemikhovskyAVX-512: Added all forms of COMPRESS instruction
2014-12-11 Jozef Kolek[mips][microMIPS] Implement CodeGen support for LI16...
2014-12-11 Michael Kuperstein[X86] When converting movs to pushes, don't assume...
2014-12-11 Elena DemikhovskyAVX-512: Fixed a bug in lowering setcc for MVT::i1...
2014-12-11 Kumar Sukhanitest commit (spelling correction)
2014-12-11 Ahmed Bougacha[X86] Add back AVX2 VR256 PMOVX patterns.
2014-12-10 Tim NorthoverARM: correctly expand LDR-lit based globals.
2014-12-10 Colin LeMahieu[Hexagon] Adding combine ri/ir instructions.
2014-12-10 Colin LeMahieu[Hexagon] Adding encodings for JR class instructions...
2014-12-10 Juergen Ributzka[AArch64] MachO large code-model: Materialize FP consta...
2014-12-10 Marek OlsakR600/SI: Use getTargetConstant in AdjustRegClass
2014-12-10 Colin LeMahieu[Hexagon] Adding JR class predicated call reg instructions.
2014-12-10 Sanjay PatelMatch new shuffle codegen for MOVHPD patterns
2014-12-10 Michael Kuperstein[X86] Make a code path in EltsFromConsecutiveLoads...
2014-12-10 Ahmed Bougacha[ARM] Combine base-updating/post-incrementing vector...
2014-12-09 Colin LeMahieu[Hexagon] [NFC] Cleaning up unused classes.
2014-12-09 Ahmed Bougacha[ARM] Factor out base-updating VLD/VST combiner functio...
2014-12-09 Ahmed Bougacha[ARM] Move the store combiner function down. NFC.
2014-12-09 Ahmed Bougacha[ARM] Also support v2f64 vld1/vst1.
2014-12-09 Colin LeMahieu[Hexagon] Fixing broken tests.
2014-12-09 Colin LeMahieu[Hexagon] Updating rr/ri 32/64 transfer encodings and...
2014-12-09 Juergen Ributzka[FastISel][AArch64] Fix a missing nullptr check in...
2014-12-09 Colin LeMahieu[Hexagon] Adding word combine dot-new form and replacin...
2014-12-09 Robert Khasanov[AVX512] Added lowering for VBROADCASTSS/SD instructions.
2014-12-09 Duncan P. N. Exon... IR: Split Metadata from Value
2014-12-09 Colin LeMahieu[Hexagon] Updating predicate register transfers and...
2014-12-09 Bill Schmidt[PowerPC 4/4] Enable little-endian support for VSX.
2014-12-09 Bill Schmidt[PowerPC 3/4] Little-endian adjustments for VSX vector...
2014-12-09 Bill Schmidt[PowerPC 2/4] Little-endian adjustments for VSX insert...
2014-12-09 Robert Khasanov[AVX512] Added VPBROADCAST{BWDQ} (Load with Broadcast...
2014-12-09 Bill Schmidt[PowerPC 1/4] Little-endian adjustments for VSX loads...
2014-12-09 Chandler Carruth[x86] Fix the test to actually test things for the...
2014-12-09 Aaron BallmanRemoving an unused variable to silence a -Wunused-but...
2014-12-09 Asiri RathnayakeFix modified immediate bug reported by MC Hammer.
2014-12-09 Chandler Carruth[x86] Bring some sanity to the x86 CPU processor defini...
2014-12-09 Elena DemikhovskyAVX-512: Added some comments to ERI scalar intrinsics.
2014-12-09 Mohit K. Bhakkadtest commit (spelling correction)
2014-12-09 Michael Kuperstein[X86] Convert esp-relative movs of function arguments...
2014-12-09 Bill SchmidtRestore r223709 as it was meant to be, and enable Featu...
2014-12-09 NAKAMURA TakumiRevert r223709, "[PowerPC]Activate FeatureVSX for the...
2014-12-09 Tom StellardR600/SI: Set MayStore = 0 on MUBUF loads
2014-12-09 Tom StellardR600/SI: Move setting of the lds bit to the base MUBUF...
2014-12-08 Colin LeMahieu[Hexagon] Removing old def versions and replacing usage...
2014-12-08 Colin LeMahieu[Hexagon] Adding any8, all8, and/or/xor/andn/orn/not...
2014-12-08 Bill Seurer[PowerPC]Activate FeatureVSX for the Power target
2014-12-08 Hal Finkel[PowerPC] Don't use a non-allocatable register to imple...
2014-12-08 Colin LeMahieu[Hexagon] Adding xtype doubleword add, sub, and, or...
2014-12-08 Colin LeMahieu[Hexagon] Adding xtype doubleword comparisons. Removin...
2014-12-08 Colin LeMahieu[Hexagon] Adding xtype parity, min, minu, max, maxu...
2014-12-08 Colin LeMahieu[Hexagon] Adding xtype halfword add/sub ll/hl/lh/hh...
2014-12-08 Matt ArsenaultR600/SI: Move continue after checking s_mov_b32.
2014-12-08 Colin LeMahieu[Hexagon] Adding add/sub with saturation. Removing...
2014-12-08 Bruno Cardoso Lopes[CompactUnwind] Fix register encoding logic
2014-12-08 Tim NorthoverAArch64: treat HFAs containing "half" types as blocks...
2014-12-08 Andrea Di Biagio[X86] Improved tablegen patters for matching TZCNT...
2014-12-08 Colin LeMahieu[Hexagon] Adding combine reg, reg with predicated forms.
2014-12-08 Colin LeMahieu[Hexagon] Adding packhl instruction.
2014-12-08 Daniel Sanders[mips] Add Mips-specific CCIf's for accessing the MipsC...
2014-12-08 Andrea Di Biagio[X86] Improved lowering of packed v8i16 vector shifts...
2014-12-08 Elena DemikhovskyX86 intrinsics moved form X86ISelLowering.cpp to X86Int...
2014-12-07 Marek OlsakR600/SI: Disable VMEM and SMEM clauses by breaking...
2014-12-07 Marek OlsakR600/SI: Set 20-bit immediate byte offset for SMRD...
2014-12-07 Marek OlsakR600/SI: Update instruction conversions for VI
2014-12-07 Marek OlsakR600/SI: Add VI instructions
2014-12-07 Marek OlsakR600/SI: Add SCC Defs/Uses to SOP1 and SOP2 opcodes
2014-12-06 Benjamin KramerMake the DenseMap bucket type configurable and use...
2014-12-06 Tom StellardR600/SI: Restore PrivateGlobalPrefix to the default...
2014-12-06 Ahmed Bougacha[X86] Refactor PMOV[SZ]Xrm to add missing AVX2 patterns.
2014-12-06 Tim NorthoverAArch64: use explicit MVT::i64 when creating EXTRACT_SU...
2014-12-05 Ahmed Bougacha[X86] Cleanup FCOPYSIGN lowering. NFC intended.
2014-12-05 Colin LeMahieu[Hexagon] Relocating logical instructions and templates...
2014-12-05 Colin LeMahieu[Hexagon] Adding sub/and/or reg, imm forms
2014-12-05 Sanjay PatelOptimize merging of scalar loads for 32-byte vectors...
2014-12-05 Colin LeMahieu[Hexagon] Updating mux_ir/ri/ii/rr with encoding bits
2014-12-05 Jan Wen VoungUse 32-bit ebp for NaCl64 in a limited case: llvm.frame...
2014-12-05 Bill Seurer[PowerPC]Add VSX loads/stores to fastisel for PPC target
2014-12-05 Colin LeMahieu[Hexagon] Adding tfrih/l instructions.
2014-12-05 Andrea Di Biagio[X86] Improved lowering of packed vector shifts to...
2014-12-05 Colin LeMahieu[Hexagon] Adding add reg, imm form with encoding bits...
2014-12-05 Colin LeMahieu[Hexagon] Adding DoubleRegs decoder. Moving C2_mux...
2014-12-05 Colin LeMahieu[Hexagon] [NFC] Rearranging patterns and mux instruction.
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