ARM sched model: Add SIMD/VFP load/store instructions on Swift
[oota-llvm.git] / lib / Target /
2013-06-04 Arnold SchwaighoferARM sched model: Add SIMD/VFP load/store instructions...
2013-06-04 Arnold SchwaighoferARM sched model: Add integer VFP/SIMD instructions...
2013-06-04 Arnold SchwaighoferARM sched model: Add integer load/store instructions...
2013-06-04 Arnold SchwaighoferARM sched model: Add integer arithmetic instructions...
2013-06-04 Arnold SchwaighoferARM sched model: Cortex A9 - More InstRW sched resources
2013-06-04 Arnold SchwaighoferARM sched model: Add branch thumb instructions
2013-06-04 Arnold SchwaighoferARM sched model: Add branch thumb2 instructions
2013-06-04 Arnold SchwaighoferARM sched model: Add branch instructions
2013-06-04 Arnold SchwaighoferARM sched model: Add preload thumb2 instructions
2013-06-04 Arnold SchwaighoferARM sched model: Add preload instructions
2013-06-04 Arnold SchwaighoferARM sched model: Add more ALU and CMP thumb instructions
2013-06-04 Arnold Schwaighofer ARM sched model: Add more ALU and CMP thumb2 instructions
2013-06-04 Arnold SchwaighoferARM sched model: Add more ALU and CMP instructions
2013-06-04 Arnold SchwaighoferARM sched model: Add divsion, loads, branches, vfp cvt
2013-06-04 Arnold SchwaighoferARMInstrInfo: Improve isSwiftFastImmShift
2013-06-04 Venkatraman Govind... Sparc: No functionality change. Cleanup whitespaces...
2013-06-04 David MajnemerARM: Fix crash in ARM backend inside of ARMConstantIsla...
2013-06-04 Vincent LejeuneR600: Swizzle texture/export instructions
2013-06-04 Vladimir MedicTest commit for user vmedic, to verify commit access...
2013-06-04 Aaron BallmanSilencing an MSVC warning about mixing bool and unsigne...
2013-06-03 Tom StellardR600/SI: Add support for work item and work group intri...
2013-06-03 Tom StellardR600/SI: Add a calling convention for compute shaders
2013-06-03 Tom StellardR600/SI: Custom lower i64 sign_extend
2013-06-03 Tom StellardR600/SI: Adjust some instructions' out register class...
2013-06-03 Tom StellardR600/SI: Handle REG_SEQUENCE in fitsRegClass()
2013-06-03 Tom StellardR600/SI: Handle nodes with glue results correctly SITar...
2013-06-03 Tom StellardR600/SI: Fixup CopyToReg register class in PostprocessI...
2013-06-03 Tom StellardR600/SI: Add support for global loads
2013-06-03 Tom StellardR600/SI: Rework MUBUF store instructions
2013-06-03 Vincent LejeuneR600: 3 op instructions have no write bit but the resul...
2013-06-03 Vincent LejeuneR600: CALL_FS consumes a stack size entry
2013-06-03 Vincent LejeuneR600: use capital letter for PV channel
2013-06-03 Vincent LejeuneR600: Constraints input regs of interp_xy,_zw
2013-06-03 Ahmed BougachaX86: sub_xmm registers are 128 bits wide.
2013-06-03 Venkatraman Govind... Sparc: Add support for indirect branch and blockaddress...
2013-06-03 Venkatraman Govind... Sparc: When storing 0, use %g0 directly in the store...
2013-06-02 Venkatraman Govind... Sparc: Combine add/or/sethi instruction with restore...
2013-06-02 Venkatraman Govind... Sparc: Perform leaf procedure optimization by default
2013-06-01 Venkatraman Govind... Sparc: Mark functions calling llvm.vastart and llvm...
2013-06-01 Tim NorthoverRevert r183069: "TMP: LEA64_32r fixing"
2013-06-01 Tim NorthoverTMP: LEA64_32r fixing
2013-06-01 Tim NorthoverX86: change MOV64ri64i32 into MOV32ri64
2013-06-01 Venkatraman Govind... [Sparc] Generate correct code for leaf functions with...
2013-05-31 Ahmed BougachaMake SubRegIndex size mandatory, following r183020.
2013-05-31 Eric ChristopherTemporarily Revert "X86: change MOV64ri64i32 into MOV32...
2013-05-31 Benjamin KramerNVPTX: Don't even create a regalloc if we're not going...
2013-05-31 Ahmed BougachaAdd a way to define the bit range covered by a SubRegIndex.
2013-05-31 Tim NorthoverARM: permit upper-case BE/LE on setend instruction
2013-05-31 Tim NorthoverARM: add fstmx and fldmx instructions for assembly
2013-05-31 Tim NorthoverARM: fix VEXT encoding corner case
2013-05-31 Richard Sandiford[SystemZ] Don't use LOAD and STORE REVERSED for volatil...
2013-05-31 Justin Holewinski[NVPTX] Re-enable support for virtual registers in...
2013-05-31 Tim NorthoverX86: change MOV64ri64i32 into MOV32ri64
2013-05-31 Akira Hatanaka[mips] Big-endian code generation for atomic instructions.
2013-05-30 Rafael EspindolaRevert r182937 and r182877.
2013-05-30 Tim NorthoverX86: use sub-register sequences for MOV*r0 operations
2013-05-30 Justin Holewinski[NVPTX] Fix case where a sext load of an i1 type may...
2013-05-30 Tim NorthoverX86: change zext moves to use sub-register infrastructure.
2013-05-30 Richard Sandiford[SystemZ] Enable unaligned accesses
2013-05-29 Andrew TrickOrder CALLSEQ_START and CALLSEQ_END nodes.
2013-05-29 Ahmed BougachaX86: Fix Defs/Uses for insts that imp-def/imp-use both...
2013-05-29 Chad RosierDon't assume the registers will be enumerated sequentially.
2013-05-29 JF BastienEnable FastISel on ARM for Linux and NaCl
2013-05-29 Bill WendlingDon't reach into the middle of TargetMachine and cache...
2013-05-29 JF BastienTidy some register classes for ARM and Thumb
2013-05-29 NAKAMURA TakumiSparcFrameLowering.cpp: Mark verifyLeafProcRegUse(...
2013-05-29 Richard Sandiford[SystemZ] Immediate compare-and-branch support
2013-05-29 Patrik HagglundTemporary fix to get rid of gcc warning.
2013-05-29 Venkatraman Govind... [Sparc] Add support for leaf functions in sparc backend.
2013-05-28 Jack CarterMips assembler: Improve set register alias handling
2013-05-28 Tim NorthoverAArch64: clarify -help message
2013-05-28 Jyotsna VermaHexagon: Typo fix.
2013-05-28 Richard Sandiford[SystemZ] Register compare-and-branch support
2013-05-28 Richard Sandiford[SystemZ] Tweak SystemZInstrInfo::isBranch() interface
2013-05-27 Rafael EspindolaMake helper functions static.
2013-05-27 Preston GurdConvert sqrt functions into sqrt instructions when...
2013-05-27 Hal FinkelPPC: Add a isConsecutiveLS utility function
2013-05-26 Hal FinkelPrefer to duplicate PPC Altivec loads when expanding...
2013-05-25 Hal FinkelPPC: Combine duplicate (offset) lvsl Altivec intrinsics
2013-05-25 Andrew TrickTrack IR ordering of SelectionDAG nodes 3/4.
2013-05-25 Andrew TrickTrack IR ordering of SelectionDAG nodes 2/4.
2013-05-24 Hal FinkelPPC: Initial support for permutation-based unaligned...
2013-05-24 Quentin ColombetFollow up of the introduction of MCSymbolizer.
2013-05-24 Michael J. SpencerReplace Count{Leading,Trailing}Zeros_{32,64} with count...
2013-05-24 Richard Sandiford[SystemZ] Improve AsmParser handling of invalid instruc...
2013-05-24 Richard Sandiford[SystemZ] Improve AsmParser register parsing
2013-05-24 Benjamin KramerRemove the Copied parameter from MemoryObject::readBytes.
2013-05-24 Ahmed BougachaMC: Disassembled CFG reconstruction.
2013-05-24 Ahmed BougachaAdd MCSymbolizer for symbolic/annotated disassembly.
2013-05-23 Ulrich Weigand[PowerPC] Remove symbolLo/symbolHi instruction operand...
2013-05-23 Ulrich Weigand[PowerPC] Clean up generation of ha16() / lo16() markers
2013-05-23 Tim NorthoverARM: implement @llvm.readcyclecounter intrinsic
2013-05-23 Tim NorthoverARM: Add Performance Monitor Extensions feature
2013-05-23 Tom StellardR600: Fix R600ControlFlowFinalizer not considering...
2013-05-23 Benjamin KramerMove passes from namespace llvm into anonymous namespac...
2013-05-23 Benjamin KramerMore symbols that should be static.
2013-05-23 Benjamin KramerHexagon: Make helper functions static.
2013-05-23 Benjamin KramerR600: Hide symbols of implementation details.
2013-05-23 Aaron BallmanSetting the default value (fixes CRT assertions about...
2013-05-23 Rafael EspindolaFix 32 bit build in c++11 mode.
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