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R600: Move Subtarget feature definitions into AMDGPU.td
[oota-llvm.git] / lib /
2013-06-07 Tom StellardR600: Move Subtarget feature definitions into AMDGPU.td tree | commitdiff
2013-06-07 Tom StellardR600: Remove unnecessary include tree | commitdiff
2013-06-07 Quentin ColombetAdd a backend option to warn on a given stack size... tree | commitdiff
2013-06-07 JF BastienARM FastISel integer sext/zext improvements tree | commitdiff
2013-06-07 Benjamin KramerR600: Don't compare iterators of different maps. tree | commitdiff
2013-06-07 Quentin ColombetTeach AsmPrinter how to print odd constants. tree | commitdiff
2013-06-07 Manman RenDIBuilder: No functionality change. tree | commitdiff
2013-06-07 Benjamin KramerVincent says the element is at most once in the vector... tree | commitdiff
2013-06-07 Rafael EspindolaUse isxdigit. tree | commitdiff
2013-06-07 Roman DivackyFix a typo in asm string of BP* family of instructions... tree | commitdiff
2013-06-07 Rafael EspindolaSupport OpenBSD's native frame protection conventions. tree | commitdiff
2013-06-07 Benjamin KramerR600: Fix a potential iterator invalidation issue. tree | commitdiff
2013-06-07 Vincent LejeuneR600: Remove an extra break in R600OptimizeVectorRegist... tree | commitdiff
2013-06-07 Benjamin KramerFold variable that's only used in assert into the assert. tree | commitdiff
2013-06-07 Duncan SandsCorrect wrong register in this example, pointed out... tree | commitdiff
2013-06-07 Bill WendlingDon't cache the instruction and register info from... tree | commitdiff
2013-06-07 Bill WendlingDon't cache the instruction and register info from... tree | commitdiff
2013-06-07 Bill WendlingDon't cache the instruction and register info from... tree | commitdiff
2013-06-07 Bill WendlingDon't cache the instruction and register info from... tree | commitdiff
2013-06-07 Bill WendlingDon't cache the instruction and register info from... tree | commitdiff
2013-06-07 Michael Gottesman[objc-arc] Ensure that the cfg path count does not... tree | commitdiff
2013-06-07 Bill WendlingDon't cache the instruction and register info from... tree | commitdiff
2013-06-07 Bill WendlingDon't cache the instruction info and register info... tree | commitdiff
2013-06-07 Manman RenDIBuilder: No functionality change. tree | commitdiff
2013-06-07 Arnold SchwaighoferARM sched model: Use the right resources for DIV tree | commitdiff
2013-06-07 Arnold SchwaighoferARM sched model: Add VFP div instruction on Swift tree | commitdiff
2013-06-07 Arnold SchwaighoferARM sched model: Add SIMD/VFP load/store instructions... tree | commitdiff
2013-06-07 Venkatraman Govind... [Sparc]: Use cmp instruction instead of subcc to compar... tree | commitdiff
2013-06-06 Jakub StaszakSimplify code. No functionality change. tree | commitdiff
2013-06-06 Vincent LejeuneR600: Rewrite an awkward loop in R600MachineScheduler tree | commitdiff
2013-06-06 Nadav RotemJeffrey Yasskin volunteered to benchmark the vectorizer... tree | commitdiff
2013-06-06 David BlaikieFix break in r183446 - helps to increment the iterator... tree | commitdiff
2013-06-06 Arnold SchwaighoferRevert "ARM sched model: Add SIMD/VFP load/store instru... tree | commitdiff
2013-06-06 David BlaikieDebug Info: simplify parameter ordering preservation tree | commitdiff
2013-06-06 Arnold SchwaighoferARM sched model: Add SIMD/VFP load/store instructions... tree | commitdiff
2013-06-06 Arnold SchwaighoferARM sched model: Add integer VFP/SIMD instructions... tree | commitdiff
2013-06-06 Jakub StaszakRe-apply "Use IRBuilder instead of ConstantInt methods... tree | commitdiff
2013-06-06 Arnold SchwaighoferARM sched model: Add integer load/store instructions... tree | commitdiff
2013-06-06 Arnold SchwaighoferARM sched model: Add integer arithmetic instructions... tree | commitdiff
2013-06-06 Arnold SchwaighoferARM sched model: Cortex A9 - More InstRW sched resources tree | commitdiff
2013-06-06 Arnold SchwaighoferARM sched model: Add branch thumb instructions tree | commitdiff
2013-06-06 Arnold SchwaighoferARM sched model: Add branch thumb2 instructions tree | commitdiff
2013-06-06 Arnold SchwaighoferARM sched model: Add branch instructions tree | commitdiff
2013-06-06 Arnold SchwaighoferARM sched model: Add preload thumb2 instructions tree | commitdiff
2013-06-06 Arnold SchwaighoferARM sched model: Add preload instructions tree | commitdiff
2013-06-06 Kevin EnderbyTeach llvm-objdump with the -macho parser how to use... tree | commitdiff
2013-06-06 Arnold SchwaighoferARM sched model: Add more ALU and CMP thumb instructions tree | commitdiff
2013-06-06 Rafael EspindolaRevert "Use IRBuilder instead of ConstantInt methods... tree | commitdiff
2013-06-06 Arnold SchwaighoferARM sched model: Add more ALU and CMP thumb2 instructions tree | commitdiff
2013-06-06 Vincent LejeuneR600: Remove leftover code in R600MachineScheduler.cpp tree | commitdiff
2013-06-06 Rafael EspindolaPrint symbol names in relocations when dumping COFF... tree | commitdiff
2013-06-06 Bill WendlingCast to the correct type. Pointer, not reference. tree | commitdiff
2013-06-06 NAKAMURA TakumiR600OptimizeVectorRegisters.cpp: Tweak a warning. ... tree | commitdiff
2013-06-06 NAKAMURA TakumiR600OptimizeVectorRegisters.cpp: Suppress a warning... tree | commitdiff
2013-06-06 NAKAMURA TakumiTrailing linefeed. tree | commitdiff
2013-06-06 Bill WendlingCast to the proper type. tree | commitdiff
2013-06-06 Jakub StaszakRemove unneeded cast<>. tree | commitdiff
2013-06-06 Bill WendlingCache the TargetLowering info object as a pointer. tree | commitdiff
2013-06-06 Jakub StaszakUse IRBuilder instead of ConstantInt methods. tree | commitdiff
2013-06-06 Bill WendlingDon't cache the TargetLoweringInfo object inside of... tree | commitdiff
2013-06-05 Sean SilvaAdd writeAsHex(raw_ostream &) method to BinaryRef. tree | commitdiff
2013-06-05 Tom StellardR600: Replace predicate loop with predicate function tree | commitdiff
2013-06-05 Sean SilvaRename BinaryRef::isBinary to more descriptive DataIsHe... tree | commitdiff
2013-06-05 Bill WendlingAdd space to assert message. tree | commitdiff
2013-06-05 Sean SilvaAdd writeAsBinary(raw_ostream &) method to BinaryRef. tree | commitdiff
2013-06-05 Vincent LejeuneR600: Add a pass that merge Vector Register tree | commitdiff
2013-06-05 Vincent LejeuneR600: Schedule copy from phys register at beginning... tree | commitdiff
2013-06-05 Akira Hatanaka[mips] brcond + setgt/setugt instruction selection... tree | commitdiff
2013-06-05 Jakub StaszakUse IRBuilder instead of ConstantInt methods. It simpli... tree | commitdiff
2013-06-05 Michael Liao[PATCH] Fix VGATHER* operand constraints tree | commitdiff
2013-06-05 Arnold SchwaighoferARM sched model: Add more ALU and CMP instructions tree | commitdiff
2013-06-05 Arnold SchwaighoferARM sched model: Add divsion, loads, branches, vfp cvt tree | commitdiff
2013-06-05 Arnold SchwaighoferARMInstrInfo: Improve isSwiftFastImmShift tree | commitdiff
2013-06-05 Mihai PopaThis is a simple patch that changes RRX and RRXS to... tree | commitdiff
2013-06-05 David BlaikiePR15662: Optimized debug info produces out of order... tree | commitdiff
2013-06-05 Tom StellardR600: Make sure to schedule AR register uses and defs... tree | commitdiff
2013-06-05 Rafael EspindolaDon't print default values for NumberOfAuxSymbols and... tree | commitdiff
2013-06-05 Rafael EspindolaHandle (at least don't crash on) relocations with no... tree | commitdiff
2013-06-05 Rafael EspindolaMove BinaryRef to a new include/llvm/Object/YAML.h... tree | commitdiff
2013-06-05 Rafael EspindolaRevert "R600: Add a pass that merge Vector Register" tree | commitdiff
2013-06-05 Rafael EspindolaHandle relocations that don't point to symbols. tree | commitdiff
2013-06-04 Vincent LejeuneR600: Add a pass that merge Vector Register tree | commitdiff
2013-06-04 Vincent LejeuneR600: Const/Neg/Abs can be folded to dot4 tree | commitdiff
2013-06-04 Evan ChengCortex-R5 can issue Thumb2 integer division instructions. tree | commitdiff
2013-06-04 Arnold SchwaighoferRevert series of sched model patches until I figure... tree | commitdiff
2013-06-04 Arnold SchwaighoferARM sched model: Add VFP div instruction on Swift tree | commitdiff
2013-06-04 Arnold SchwaighoferARM sched model: Add SIMD/VFP load/store instructions... tree | commitdiff
2013-06-04 Arnold SchwaighoferARM sched model: Add integer VFP/SIMD instructions... tree | commitdiff
2013-06-04 Arnold SchwaighoferARM sched model: Add integer load/store instructions... tree | commitdiff
2013-06-04 Arnold SchwaighoferARM sched model: Add integer arithmetic instructions... tree | commitdiff
2013-06-04 Arnold SchwaighoferARM sched model: Cortex A9 - More InstRW sched resources tree | commitdiff
2013-06-04 Arnold SchwaighoferARM sched model: Add branch thumb instructions tree | commitdiff
2013-06-04 Arnold SchwaighoferARM sched model: Add branch thumb2 instructions tree | commitdiff
2013-06-04 Arnold SchwaighoferARM sched model: Add branch instructions tree | commitdiff
2013-06-04 Arnold SchwaighoferARM sched model: Add preload thumb2 instructions tree | commitdiff
2013-06-04 Arnold SchwaighoferARM sched model: Add preload instructions tree | commitdiff
2013-06-04 Arnold SchwaighoferARM sched model: Add more ALU and CMP thumb instructions tree | commitdiff
2013-06-04 Arnold Schwaighofer ARM sched model: Add more ALU and CMP thumb2 instructions tree | commitdiff
2013-06-04 Arnold SchwaighoferARM sched model: Add more ALU and CMP instructions tree | commitdiff
2013-06-04 Arnold SchwaighoferARM sched model: Add divsion, loads, branches, vfp cvt tree | commitdiff
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C/C++ LLVM-based compilers that forbids OOTA behaviors