2013-06-07 |
Bill Wendling | Don't cache the instruction and register info from... |
tree | commitdiff |
2013-06-07 |
Bill Wendling | Don't cache the instruction and register info from... |
tree | commitdiff |
2013-06-07 |
Michael Gottesman | [objc-arc] Ensure that the cfg path count does not... |
tree | commitdiff |
2013-06-07 |
Bill Wendling | Don't cache the instruction and register info from... |
tree | commitdiff |
2013-06-07 |
Bill Wendling | Don't cache the instruction info and register info... |
tree | commitdiff |
2013-06-07 |
Manman Ren | DIBuilder: No functionality change. |
tree | commitdiff |
2013-06-07 |
Arnold Schwaighofer | ARM sched model: Use the right resources for DIV |
tree | commitdiff |
2013-06-07 |
Arnold Schwaighofer | ARM sched model: Add VFP div instruction on Swift |
tree | commitdiff |
2013-06-07 |
Arnold Schwaighofer | ARM sched model: Add SIMD/VFP load/store instructions... |
tree | commitdiff |
2013-06-07 |
Venkatraman Govind... | [Sparc]: Use cmp instruction instead of subcc to compar... |
tree | commitdiff |
2013-06-06 |
Jakub Staszak | Simplify code. No functionality change. |
tree | commitdiff |
2013-06-06 |
Vincent Lejeune | R600: Rewrite an awkward loop in R600MachineScheduler |
tree | commitdiff |
2013-06-06 |
Nadav Rotem | Jeffrey Yasskin volunteered to benchmark the vectorizer... |
tree | commitdiff |
2013-06-06 |
David Blaikie | Fix break in r183446 - helps to increment the iterator... |
tree | commitdiff |
2013-06-06 |
Arnold Schwaighofer | Revert "ARM sched model: Add SIMD/VFP load/store instru... |
tree | commitdiff |
2013-06-06 |
David Blaikie | Debug Info: simplify parameter ordering preservation |
tree | commitdiff |
2013-06-06 |
Arnold Schwaighofer | ARM sched model: Add SIMD/VFP load/store instructions... |
tree | commitdiff |
2013-06-06 |
Arnold Schwaighofer | ARM sched model: Add integer VFP/SIMD instructions... |
tree | commitdiff |
2013-06-06 |
Jakub Staszak | Re-apply "Use IRBuilder instead of ConstantInt methods... |
tree | commitdiff |
2013-06-06 |
Arnold Schwaighofer | ARM sched model: Add integer load/store instructions... |
tree | commitdiff |
2013-06-06 |
Arnold Schwaighofer | ARM sched model: Add integer arithmetic instructions... |
tree | commitdiff |
2013-06-06 |
Arnold Schwaighofer | ARM sched model: Cortex A9 - More InstRW sched resources |
tree | commitdiff |
2013-06-06 |
Arnold Schwaighofer | ARM sched model: Add branch thumb instructions |
tree | commitdiff |
2013-06-06 |
Arnold Schwaighofer | ARM sched model: Add branch thumb2 instructions |
tree | commitdiff |
2013-06-06 |
Arnold Schwaighofer | ARM sched model: Add branch instructions |
tree | commitdiff |
2013-06-06 |
Arnold Schwaighofer | ARM sched model: Add preload thumb2 instructions |
tree | commitdiff |
2013-06-06 |
Arnold Schwaighofer | ARM sched model: Add preload instructions |
tree | commitdiff |
2013-06-06 |
Kevin Enderby | Teach llvm-objdump with the -macho parser how to use... |
tree | commitdiff |
2013-06-06 |
Arnold Schwaighofer | ARM sched model: Add more ALU and CMP thumb instructions |
tree | commitdiff |
2013-06-06 |
Rafael Espindola | Revert "Use IRBuilder instead of ConstantInt methods... |
tree | commitdiff |
2013-06-06 |
Arnold Schwaighofer | ARM sched model: Add more ALU and CMP thumb2 instructions |
tree | commitdiff |
2013-06-06 |
Vincent Lejeune | R600: Remove leftover code in R600MachineScheduler.cpp |
tree | commitdiff |
2013-06-06 |
Rafael Espindola | Print symbol names in relocations when dumping COFF... |
tree | commitdiff |
2013-06-06 |
Bill Wendling | Cast to the correct type. Pointer, not reference. |
tree | commitdiff |
2013-06-06 |
NAKAMURA Takumi | R600OptimizeVectorRegisters.cpp: Tweak a warning. ... |
tree | commitdiff |
2013-06-06 |
NAKAMURA Takumi | R600OptimizeVectorRegisters.cpp: Suppress a warning... |
tree | commitdiff |
2013-06-06 |
NAKAMURA Takumi | Trailing linefeed. |
tree | commitdiff |
2013-06-06 |
Bill Wendling | Cast to the proper type. |
tree | commitdiff |
2013-06-06 |
Jakub Staszak | Remove unneeded cast<>. |
tree | commitdiff |
2013-06-06 |
Bill Wendling | Cache the TargetLowering info object as a pointer. |
tree | commitdiff |
2013-06-06 |
Jakub Staszak | Use IRBuilder instead of ConstantInt methods. |
tree | commitdiff |
2013-06-06 |
Bill Wendling | Don't cache the TargetLoweringInfo object inside of... |
tree | commitdiff |
2013-06-05 |
Sean Silva | Add writeAsHex(raw_ostream &) method to BinaryRef. |
tree | commitdiff |
2013-06-05 |
Tom Stellard | R600: Replace predicate loop with predicate function |
tree | commitdiff |
2013-06-05 |
Sean Silva | Rename BinaryRef::isBinary to more descriptive DataIsHe... |
tree | commitdiff |
2013-06-05 |
Bill Wendling | Add space to assert message. |
tree | commitdiff |
2013-06-05 |
Sean Silva | Add writeAsBinary(raw_ostream &) method to BinaryRef. |
tree | commitdiff |
2013-06-05 |
Vincent Lejeune | R600: Add a pass that merge Vector Register |
tree | commitdiff |
2013-06-05 |
Vincent Lejeune | R600: Schedule copy from phys register at beginning... |
tree | commitdiff |
2013-06-05 |
Akira Hatanaka | [mips] brcond + setgt/setugt instruction selection... |
tree | commitdiff |
2013-06-05 |
Jakub Staszak | Use IRBuilder instead of ConstantInt methods. It simpli... |
tree | commitdiff |
2013-06-05 |
Michael Liao | [PATCH] Fix VGATHER* operand constraints |
tree | commitdiff |
2013-06-05 |
Arnold Schwaighofer | ARM sched model: Add more ALU and CMP instructions |
tree | commitdiff |
2013-06-05 |
Arnold Schwaighofer | ARM sched model: Add divsion, loads, branches, vfp cvt |
tree | commitdiff |
2013-06-05 |
Arnold Schwaighofer | ARMInstrInfo: Improve isSwiftFastImmShift |
tree | commitdiff |
2013-06-05 |
Mihai Popa | This is a simple patch that changes RRX and RRXS to... |
tree | commitdiff |
2013-06-05 |
David Blaikie | PR15662: Optimized debug info produces out of order... |
tree | commitdiff |
2013-06-05 |
Tom Stellard | R600: Make sure to schedule AR register uses and defs... |
tree | commitdiff |
2013-06-05 |
Rafael Espindola | Don't print default values for NumberOfAuxSymbols and... |
tree | commitdiff |
2013-06-05 |
Rafael Espindola | Handle (at least don't crash on) relocations with no... |
tree | commitdiff |
2013-06-05 |
Rafael Espindola | Move BinaryRef to a new include/llvm/Object/YAML.h... |
tree | commitdiff |
2013-06-05 |
Rafael Espindola | Revert "R600: Add a pass that merge Vector Register" |
tree | commitdiff |
2013-06-05 |
Rafael Espindola | Handle relocations that don't point to symbols. |
tree | commitdiff |
2013-06-04 |
Vincent Lejeune | R600: Add a pass that merge Vector Register |
tree | commitdiff |
2013-06-04 |
Vincent Lejeune | R600: Const/Neg/Abs can be folded to dot4 |
tree | commitdiff |
2013-06-04 |
Evan Cheng | Cortex-R5 can issue Thumb2 integer division instructions. |
tree | commitdiff |
2013-06-04 |
Arnold Schwaighofer | Revert series of sched model patches until I figure... |
tree | commitdiff |
2013-06-04 |
Arnold Schwaighofer | ARM sched model: Add VFP div instruction on Swift |
tree | commitdiff |
2013-06-04 |
Arnold Schwaighofer | ARM sched model: Add SIMD/VFP load/store instructions... |
tree | commitdiff |
2013-06-04 |
Arnold Schwaighofer | ARM sched model: Add integer VFP/SIMD instructions... |
tree | commitdiff |
2013-06-04 |
Arnold Schwaighofer | ARM sched model: Add integer load/store instructions... |
tree | commitdiff |
2013-06-04 |
Arnold Schwaighofer | ARM sched model: Add integer arithmetic instructions... |
tree | commitdiff |
2013-06-04 |
Arnold Schwaighofer | ARM sched model: Cortex A9 - More InstRW sched resources |
tree | commitdiff |
2013-06-04 |
Arnold Schwaighofer | ARM sched model: Add branch thumb instructions |
tree | commitdiff |
2013-06-04 |
Arnold Schwaighofer | ARM sched model: Add branch thumb2 instructions |
tree | commitdiff |
2013-06-04 |
Arnold Schwaighofer | ARM sched model: Add branch instructions |
tree | commitdiff |
2013-06-04 |
Arnold Schwaighofer | ARM sched model: Add preload thumb2 instructions |
tree | commitdiff |
2013-06-04 |
Arnold Schwaighofer | ARM sched model: Add preload instructions |
tree | commitdiff |
2013-06-04 |
Arnold Schwaighofer | ARM sched model: Add more ALU and CMP thumb instructions |
tree | commitdiff |
2013-06-04 |
Arnold Schwaighofer | ARM sched model: Add more ALU and CMP thumb2 instructions |
tree | commitdiff |
2013-06-04 |
Arnold Schwaighofer | ARM sched model: Add more ALU and CMP instructions |
tree | commitdiff |
2013-06-04 |
Arnold Schwaighofer | ARM sched model: Add divsion, loads, branches, vfp cvt |
tree | commitdiff |
2013-06-04 |
Arnold Schwaighofer | ARMInstrInfo: Improve isSwiftFastImmShift |
tree | commitdiff |
2013-06-04 |
Venkatraman Govind... | Sparc: No functionality change. Cleanup whitespaces... |
tree | commitdiff |
2013-06-04 |
David Majnemer | IndVarSimplify: check if loop invariant expansion can... |
tree | commitdiff |
2013-06-04 |
David Majnemer | ARM: Fix crash in ARM backend inside of ARMConstantIsla... |
tree | commitdiff |
2013-06-04 |
Vincent Lejeune | R600: Swizzle texture/export instructions |
tree | commitdiff |
2013-06-04 |
Rafael Espindola | Second part of pr16069 |
tree | commitdiff |
2013-06-04 |
Hans Wennborg | Typo: s/caes/cases/ in SimplifyCFG |
tree | commitdiff |
2013-06-04 |
Benjamin Kramer | Preserve const correctness. |
tree | commitdiff |
2013-06-04 |
Vladimir Medic | Test commit for user vmedic, to verify commit access... |
tree | commitdiff |
2013-06-04 |
Aaron Ballman | Silencing an MSVC warning about mixing bool and unsigne... |
tree | commitdiff |
2013-06-04 |
Aaron Ballman | Silencing an MSVC warning about */ being found outside... |
tree | commitdiff |
2013-06-04 |
Shuxin Yang | Fix a defect in code-layout pass, improving Benchmarks... |
tree | commitdiff |
2013-06-03 |
Nick Lewycky | Delete dead safety check. |
tree | commitdiff |
2013-06-03 |
David Majnemer | SimplifyCFG: Do not transform PHI to select if doing... |
tree | commitdiff |
2013-06-03 |
David Majnemer | SimplifyCFG: Small cleanup, use ICmpInst::isEquality() |
tree | commitdiff |
2013-06-03 |
Rafael Espindola | Update RuntimeDyldELF::findOPDEntrySection the new... |
tree | commitdiff |
2013-06-03 |
Tom Stellard | R600/SI: Add support for work item and work group intri... |
tree | commitdiff |
2013-06-03 |
Tom Stellard | R600/SI: Add a calling convention for compute shaders |
tree | commitdiff |
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