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do not compare actual branch labels; this may fix llvm-gcc-x86_64-darwin10-cross...
[oota-llvm.git]
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test
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CodeGen
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ARM
/
reg_sequence.ll
2010-09-02
Bob Wilson
Convert VLD1 and VLD2 instructions to use pseudo-instru...
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2010-08-27
Bob Wilson
Add alignment arguments to all the NEON load/store...
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2010-08-20
Bob Wilson
Replace some NEON vmovl intrinsic that I missed earlier.
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2010-07-13
Bob Wilson
Use a target-specific VMOVIMM DAG node instead of BUILD...
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2010-07-09
Bob Wilson
Print "dregpair" NEON operands with a space between...
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2010-07-09
Bob Wilson
Reenable DAG combining for vector shuffles. It looks...
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2010-06-24
Dan Gohman
Eliminate the other half of the BRCOND optimization...
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2010-06-17
Rafael Espindola
Remove arm_apcscc from the test files. It is the defaul...
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2010-05-28
Evan Cheng
Fix some latency computation bugs: if the use is not...
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2010-05-21
Evan Cheng
Change ARM scheduling default to list-hybrid if the...
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2010-05-19
Jakob Stoklund Olesen
TwoAddressInstructionPass doesn't really know how to...
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2010-05-18
Evan Cheng
Fix PR7162: Use source register classes and sub-indices...
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2010-05-17
Evan Cheng
Fix PR7175. Insert copies of a REG_SEQUENCE source...
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2010-05-17
Evan Cheng
Fix PR7156. If the sources of a REG_SEQUENCE are all...
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2010-05-17
Evan Cheng
Careful with reg_sequence coalescing to not to overwrit...
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2010-05-17
Evan Cheng
Turn on -neon-reg-sequence by default.
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