Lower AVX v4i64->v4i32 truncate to one shuffle.
[oota-llvm.git] / test / CodeGen / Mips / msa / vec.ll
2014-02-16 Nico RieckFix more broken CHECK lines
2013-10-30 Daniel Sanders[mips][msa] Added support for matching bmnz, bmnzi...
2013-09-27 Daniel Sanders[mips][msa] MSA requires FR=1 mode (64-bit FPU register...
2013-09-24 Daniel Sanders[mips][msa] Added support for matching bsel and bseli...
2013-09-23 Daniel Sanders[mips][msa] Added support for matching and, or, and...
2013-08-28 Daniel Sanders[mips][msa] Summarize tests
2013-08-27 Daniel Sanders[mips][msa] Added tests for and.v, bmnz.v, bmz.v, bsel...
2013-08-20 Daniel Sanders[mips][msa] Added and.v, bmnz.v, bmz.v, bsel.v, nor...