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R600/SI: Add intrinsic for BUFFER_LOAD_DWORD* instructions
[oota-llvm.git]
/
test
/
CodeGen
/
R600
/
fadd.ll
2013-10-10
Tom Stellard
R600/SI: Use -verify-machineinstrs for most tests
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2013-09-04
Vincent Lejeune
R600: Non vector only instruction can be scheduled...
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2013-08-16
Tom Stellard
R600: Expand vector float operations for both SI and...
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2013-08-12
Tom Stellard
R600: Set scheduling preference to Sched::Source
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2013-08-01
Tom Stellard
R600: Add 64-bit float load/store support
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2013-07-31
Tom Stellard
Revert "R600: Non vector only instruction can be schedu...
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2013-07-31
Vincent Lejeune
R600: Non vector only instruction can be scheduled...
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2013-06-05
Vincent Lejeune
R600: Schedule copy from phys register at beginning...
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2013-06-03
Vincent Lejeune
R600: use capital letter for PV channel
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2013-05-17
Vincent Lejeune
R600: Use bottom up scheduling algorithm
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2013-05-02
Vincent Lejeune
R600: Prettier asmPrint of Alu
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2013-04-19
Tom Stellard
R600: Reorganize lit tests and document how they should...
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2012-12-11
Tom Stellard
Add R600 backend
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2012-07-16
Tom Stellard
Revert "test/CodeGen/R600: Add some basic tests v6"
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2012-07-16
Tom Stellard
test/CodeGen/R600: Add some basic tests v6
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