R600/SI: Expand urem of v2i32/v4i32 for SI
[oota-llvm.git] / test / CodeGen / R600 /
2013-06-25 Aaron WatryR600/SI: Expand urem of v2i32/v4i32 for SI
2013-06-25 Aaron WatryR600/SI: Expand udiv v[24]i32 for SI and v2i32 for EG
2013-06-25 Aaron WatryR600/SI: Expand ashr of v2i32/v4i32 for SI
2013-06-25 Aaron WatryR600/SI: Expand srl of v2i32/v4i32 for SI
2013-06-25 Aaron WatryR600/SI: Expand shl of v2i32/v4i32 for SI
2013-06-25 Aaron WatryR600/SI: Expand or of v2i32/v4i32 for SI
2013-06-25 Aaron WatryR600/SI: Expand mul of v2i32/v4i32 for SI
2013-06-25 Aaron WatryR600/SI: Expand and of v2i32/v4i32 for SI
2013-06-25 Tom StellardR600/SI: Report unaligned memory accesses as legal...
2013-06-25 Tom StellardR600: Add support for i32 loads from the constant addre...
2013-06-25 Tom StellardR600/SI: Add support for v4i32 and v4f32 kernel args
2013-06-25 Tom StellardR600: Fix typo in R600Schedule.td
2013-06-20 Tom StellardR600/SI: Expand sub for v2i32 and v4i32 for SI
2013-06-20 Tom StellardR600/SI: Expand add for v2i32 and v4i32
2013-06-20 Tom StellardR600: Expand v2i32 load/store instead of custom lowering
2013-06-17 Vincent LejeuneR600: PV stores Reg id, not index
2013-06-17 Vincent LejeuneR600: Properly set COUNT_3 bit in TEX clause initiating...
2013-06-15 Tom StellardR600: Add SI load support for v[24]i32 and store for...
2013-06-14 Tom StellardR600: Use correct encoding for Vertex Fetch instruction...
2013-06-14 Tom StellardR600: Use EXPORT_RAT_INST_STORE_DWORD for stores on...
2013-06-07 Vincent LejeuneR600: Anti dep better handled in tex clause
2013-06-07 Tom StellardR600: Fix calculation of stack offset in AMDGPUFrameLow...
2013-06-07 Tom StellardR600: Fix the fetch limits for R600 generation GPUs
2013-06-05 Vincent LejeuneR600: Add a pass that merge Vector Register
2013-06-05 Vincent LejeuneR600: Schedule copy from phys register at beginning...
2013-06-05 Tom StellardR600: Make sure to schedule AR register uses and defs...
2013-06-05 Rafael EspindolaRevert "R600: Add a pass that merge Vector Register"
2013-06-04 Vincent LejeuneR600: Add a pass that merge Vector Register
2013-06-04 Vincent LejeuneR600: Const/Neg/Abs can be folded to dot4
2013-06-04 Vincent LejeuneR600: Swizzle texture/export instructions
2013-06-04 Vincent LejeuneR600: Add a test for r183108
2013-06-03 Tom StellardR600/SI: Add support for work item and work group intri...
2013-06-03 Tom StellardR600/SI: Add a calling convention for compute shaders
2013-06-03 Tom StellardR600/SI: Custom lower i64 sign_extend
2013-06-03 Tom StellardR600/SI: Add support for global loads
2013-06-03 Vincent LejeuneR600: use capital letter for PV channel
2013-05-23 Tom StellardR600: Fix R600ControlFlowFinalizer not considering...
2013-05-20 Tom StellardR600: Fix rotr.ll on non-asserts builds
2013-05-20 Tom StellardR600/SI: Add pattern for rotr
2013-05-20 Tom StellardR600: Swap the legality of rotl and rotr
2013-05-20 Tom StellardR600/SI: Add patterns for 64-bit shift operations
2013-05-17 Vincent LejeuneR600: Lower int_load_input to copyFromReg instead of...
2013-05-17 Vincent LejeuneR600: Use bottom up scheduling algorithm
2013-05-17 Vincent LejeuneR600: Use depth first scheduling algorithm
2013-05-17 Vincent LejeuneR600: Relax some vector constraints on Dot4.
2013-05-17 Vincent LejeuneR600: Improve texture handling
2013-05-17 Vincent LejeuneR600: Rename 128 bit registers.
2013-05-17 Tom StellardR600: Fix encoding for R600 family GPUs
2013-05-14 Michel DanzerR600/SI: Add lit test coverage for the remaining patter...
2013-05-10 Tom StellardR600: Remove AMDILPeeopholeOptimizer and replace optimi...
2013-05-10 Tom StellardR600: Expand SUB for v2i32/v4i32
2013-05-10 Tom StellardR600: Expand MUL for v4i32/v2i32
2013-05-10 Tom StellardR600: Expand SRA for v4i32/v2i32
2013-05-10 Tom StellardR600: Expand vselect for v4i32 and v2i32
2013-05-08 Michel DanzerR600/SI: Add lit tests for llvm.SI.imageload and llvm...
2013-05-06 Tom StellardR600: Emit config values in register / value pairs
2013-05-06 Tom StellardR600: Stop emitting the instruction type byte before...
2013-05-06 Tom StellardR600: Emit ISA for CALL_FS_* instructions
2013-05-03 Tom StellardR600: Expand vector or, shl, srl, and xor nodes
2013-05-03 Tom StellardR600: Add pattern for SHA-256 Ma function
2013-05-02 Vincent LejeuneR600: Signed literals are 64bits wide
2013-05-02 Vincent LejeuneR600: If previous bundle is dot4, PV valid chan is...
2013-05-02 Vincent LejeuneR600: Add a test to check that use_kill is emitted
2013-05-02 Vincent LejeuneR600: Prettier asmPrint of Alu
2013-04-30 Manman RenTBAA: remove !tbaa from testing cases if not used.
2013-04-30 Vincent LejeuneR600: fix loop-address.ll test
2013-04-30 Vincent LejeuneR600: use native for alu
2013-04-30 Vincent LejeuneR600: Add FetchInst bit to instruction defs to denote...
2013-04-29 Tom StellardR600: Use correct CF_END instruction on Northern Island...
2013-04-29 Tom StellardR600: Fix encoding of CF_END_{EG, R600} instructions
2013-04-26 Tom StellardR600: Initialize AMDGPUMachineFunction::ShaderType...
2013-04-24 Tom StellardR600: Use SHT_PROGBITS for the .AMDGPU.config section
2013-04-23 Vincent LejeuneR600: Use .AMDGPU.config section to emit stacksize
2013-04-23 Vincent LejeuneR600: Add CF_END
2013-04-19 Tom StellardR600: Add pattern for the BFI_INT instruction
2013-04-19 Tom StellardR600: Reorganize lit tests and document how they should...
2013-04-17 Vincent LejeuneR600: Make Export Instruction not duplicable
2013-04-15 Tom StellardR600/SI: Emit config values in register value pairs.
2013-04-15 Tom StellardR600/SI: Emit configuration value in the .AMDGPU.config...
2013-04-15 Tom StellardR600: Emit ELF formatted code rather than raw ISA.
2013-04-10 Michel DanzerR600/SI: Add pattern for AMDGPUurecip
2013-04-10 Vincent LejeuneR600: Add VTX_READ_* and RAT_WRITE_CACHELESS_* when...
2013-04-10 Christian KonigR600/SI: dynamical figure out the reg class of MIMG
2013-04-10 Christian KonigR600/SI: adjust writemask to only the used components
2013-04-10 Christian KonigR600/SI: remove image sample writemask
2013-04-05 Tom StellardR600/SI: Add support for buffer stores v2
2013-04-05 Tom StellardR600/SI: Add processor types for each SI variant
2013-04-05 Tom StellardR600/SI: Avoid generating S_MOVs with 64-bit immediates v2
2013-04-04 Vincent LejeuneR600: Take export into account when computing cf address
2013-04-03 Vincent LejeuneR600: Fix last ALU of a clause being emitted in a separ...
2013-04-01 Vincent LejeuneR600: Add support for native control flow
2013-04-01 Vincent LejeuneR600: Emit CF_ALU and use true kcache register.
2013-03-27 Christian KonigR600/SI: add SETO/SETUO patterns
2013-03-27 Christian KonigR600/SI: add cummuting of rev instructions
2013-03-27 Christian KonigR600/SI: add mulhu/mulhs patterns
2013-03-27 Christian KonigR600/SI: add srl/sha patterns for SI
2013-03-26 Christian KonigR600/SI: mark most intrinsics as readnone v2
2013-03-22 Michel DanzerR600: Fix up test/CodeGen/R600/llvm.pow.ll for r177730
2013-03-14 Vincent LejeuneR600: Factorize code handling Const Read Port limitation
2013-03-11 NAKAMURA Takumillvm/test/CodeGen/R600/schedule-*.ll: Let them require...
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