This removes TODO added in http://reviews.llvm.org/D3658
[oota-llvm.git] / test / CodeGen / R600 /
2014-06-12 Matt ArsenaultR600/SI: Use a register set to -1 for data0 on ds_inc...
2014-06-11 Matt ArsenaultR600/SI: Fix bitcast between v2i32 and f64
2014-06-11 Matt ArsenaultR600/SI: Add common 64-bit LDS atomics
2014-06-11 Matt ArsenaultR600/SI: Add 32-bit LDS atomic cmpxchg
2014-06-11 Matt ArsenaultR600/SI: Use LDS atomic inc / dec
2014-06-11 Matt ArsenaultR600/SI: Add other LDS atomic operations
2014-06-11 Matt ArsenaultR600/SI: Fix backwards names for local atomic instructions.
2014-06-11 Matt ArsenaultR600/SI: Refactor local atomics.
2014-06-11 Matt ArsenaultR600/SI: Use v_cvt_f32_ubyte* instructions
2014-06-11 Matt ArsenaultR600/SI: Fix selection failure on scalar_to_vector
2014-06-10 Matt ArsenaultR600: Use BCNT_INT for evergreen
2014-06-10 Matt ArsenaultR600/SI: Implement i64 ctpop
2014-06-10 Matt ArsenaultR600/SI: Use bcnt instruction for ctpop
2014-06-10 Matt ArsenaultR600: Handle fcopysign
2014-06-10 Matt ArsenaultR600/SI: Handle sign_extend and zero_extend to i64...
2014-06-10 Tom StellardSelectionDAG: Expand SELECT_CC to SELECT + SETCC
2014-06-09 Alp TokerReduce verbiage of lit.local.cfg files
2014-06-09 Matt ArsenaultR600/SI: Keep 64-bit not on SALU
2014-06-09 Matt ArsenaultR600: Fix selection failure for vector bswap
2014-06-09 Matt ArsenaultR600: Add more and testcases
2014-06-06 Rafael EspindolaAllow aliases to be unnamed_addr.
2014-06-05 Matt ArsenaultR600: Fix test. Using wrong check prefix.
2014-06-05 Matt ArsenaultR600/SI: Match rsq instructions
2014-05-31 Matt ArsenaultR600/SI: Fix [s|u]int_to_fp for i1
2014-05-22 Matt ArsenaultR600: Try to convert BFE back to standard bit ops when...
2014-05-22 Matt ArsenaultR600: Add dag combine for BFE
2014-05-22 Matt ArsenaultR600: Implement ComputeNumSignBitsForTargetNode for BFE
2014-05-22 Matt ArsenaultR600: Expand mul24 for GPUs without it
2014-05-22 Matt ArsenaultR600: Expand mad24 for GPUs without it
2014-05-22 Matt ArsenaultR600: Add intrinsics for mad24
2014-05-22 Matt ArsenaultR600/SI: Match fp_to_uint / uint_to_fp for f64
2014-05-21 Matt ArsenaultR600: Partially fix constant initializers for structs...
2014-05-21 Matt ArsenaultR600: Add failing testcases for constant initializers.
2014-05-16 Tom StellardR600/SI: Promote f32 SELECT to i32
2014-05-15 Tom StellardR600/SI: Only use SALU instructions for 64-bit add...
2014-05-15 Tom StellardR600/SI: Use VALU instructions for i1 ops
2014-05-14 Jay FoadRename ComputeMaskedBits to computeKnownBits. "Masked...
2014-05-13 Matt ArsenaultR600/SI: Try to fix BFE operands when moving to VALU
2014-05-12 Matt ArsenaultR600: Add mul24 intrinsics
2014-05-12 Matt ArsenaultMake SimplifyDemandedBits understand BUILD_PAIR
2014-05-10 Vincent LejeuneR600/SI: Fold fabs/fneg into src input modifier
2014-05-10 Vincent LejeuneR600/SI: Prettier display of input modifiers
2014-05-09 Tom StellardR600/SI: Teach SIInstrInfo::moveToVALU() how to move...
2014-05-09 Tom StellardR600/SI: Fix SMRD pattern for offsets > 32 bits
2014-05-09 Tom StellardR600: Expand i64 SELECT_CC
2014-05-09 Tom StellardR600: Move MIN/MAX matching from LowerOperation() to...
2014-05-05 Tom StellardR600: Expand i64 ISD:SUB
2014-05-02 Tom StellardR600: Expand vector sin and cos.
2014-05-02 Tom StellardR600: Expand TruncStore i64 -> {i16,i8}
2014-05-01 Matt ArsenaultR600/SI: Fix verifier error with pseudo store instructions.
2014-04-30 Tom StellardR600/SI: Use VALU instructions for copying i1 values
2014-04-30 Tom StellardR600/SI: Teach moveToVALU how to handle some SMRD instr...
2014-04-29 Tom StellardR600/SI: Custom lower SI_IF and SI_ELSE to avoid machin...
2014-04-29 Tom StellardR600/SI: Only select SALU instructions in the entry...
2014-04-29 Tom StellardR600: optimize the UDIVREM 64 algorithm
2014-04-23 Matt ArsenaultR600: Add a test that used to be broken that I forgot...
2014-04-22 Matt ArsenaultR600: Emit error instead of unreachable on function...
2014-04-22 Matt ArsenaultR600: Make sign_extend_inreg legal.
2014-04-18 Matt ArsenaultR600/SI: Try to use scalar BFE.
2014-04-18 Matt ArsenaultR600/SI: Match sign_extend_inreg to s_sext_i32_i8 and...
2014-04-18 Tom StellardR600/SI: Use SReg_64 instead of VSrc_64 when selecting...
2014-04-17 Tom StellardR600/SI: Stop using i128 as the resource descriptor...
2014-04-17 Matt ArsenaultR600/SI: f64 frint is legal on CI
2014-04-17 Matt ArsenaultR600/SI: Fix zext from i1 to i64
2014-04-16 Matt ArsenaultR600: Extend r600 sign_extend_inreg tests for EG
2014-04-15 Matt ArsenaultR600/SI: Print more immediates in hex format
2014-04-15 Matt ArsenaultR600/SI: Fix loads of i1
2014-04-11 Tom StellardSelectionDAG: Use helper function to improve legalizati...
2014-04-09 Matt ArsenaultR600/SI: Match not instruction.
2014-04-07 Tom StellardR600/SI: Handle INSERT_SUBREG in SIFixSGPRCopies
2014-04-07 Tom StellardR600: Match 24-bit arithmetic patterns in a Target...
2014-04-03 Tom StellardR600: Correct opcode for BFE_INT
2014-04-03 Tom StellardR600/SI: Lower 64-bit immediates using REG_SEQUENCE
2014-04-02 Tom StellardTargetLibraryInfo: Disable memcpy and memset on R600
2014-04-01 Matt ArsenaultFix missing RUN line in test
2014-04-01 Matt ArsenaultMake isSetCCEquivalent respect the TargetBooleanContents
2014-03-31 Matt ArsenaultR600: Compute masked bits for min and max
2014-03-31 Matt ArsenaultR600: Add BFE, BFI, and BFM intrinsics to help with...
2014-03-31 Tom StellardR600/SI: Lower i64 SELECT by bitcasting to a vector...
2014-03-27 Matt ArsenaultR600: Implement isZExtFree.
2014-03-27 Matt ArsenaultR600/SI: Fix unreachable with a sext_in_reg to an illeg...
2014-03-26 Matt ArsenaultR600: Add a testcase for sext_in_reg I missed.
2014-03-25 Matt ArsenaultR600: Add failing testcase for <3 x i32> stores.
2014-03-24 Matt ArsenaultR600/SI: Fix extra mov from legalizing 64-bit SALU...
2014-03-24 Matt ArsenaultR600/SI: Sub-optimial fix for 64-bit immediates with...
2014-03-24 Matt ArsenaultR600/SI: Fix 64-bit bit ops that require the VALU.
2014-03-24 Matt ArsenaultR600: Implement isNarrowingProfitable.
2014-03-24 Matt ArsenaultR600/SI: Fix 64-bit private loads.
2014-03-21 Matt ArsenaultR600/SI: Move instruction patterns to scalar versions.
2014-03-21 Tom StellardR600/SI: Handle MUBUF instructions in SIInstrInfo:...
2014-03-21 Tom StellardR600/SI: Handle S_MOV_B64 in SIInstrInfo::moveToVALU()
2014-03-19 Matt ArsenaultR600/SI: Add support for 64-bit LDS writes
2014-03-19 Matt ArsenaultR600/SI: Add support for 64-bit LDS loads.
2014-03-19 Matt ArsenaultR600/SI: Match i16 immediate offset of LDS instructions.
2014-03-19 Matt ArsenaultR600/SI: Fix test checking wrong instruction operand.
2014-03-19 Matt ArsenaultR600/SI: Don't display the GDS bit.
2014-03-18 NAKAMURA TakumiCodeGen/R600/v_cndmask.ll: Relax an expression to unbre...
2014-03-17 Kevin EnderbyMaking a guess to fix the test case with r204056 to...
2014-03-17 Matt ArsenaultR600: Match sign_extend_inreg to BFE instructions
2014-03-17 Tom StellardR600/SI: Fix implementation of isInlineConstant() used...
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