Hexagon: Add support for lowering block address.
[oota-llvm.git] / test / CodeGen / R600 /
2013-03-05 Vincent LejeuneR600: Turn BUILD_VECTOR into Reg_Sequence
2013-03-05 Vincent LejeuneR600: Use MUL_IEEE for trig/fdiv intrinsic
2013-03-01 Christian KonigR600/SI: fix sampler tests after fixing wait insertions
2013-02-21 Tom StellardR600: Fix for Unigine when MachineSched is enabled
2013-02-21 Michel DanzerR600/SI: Make sure M0 is loaded for V_INTERP_MOV_F32
2013-02-18 Vincent LejeuneR600/SI: Use MULADD_IEEE/V_MAD_F32 instruction for...
2013-02-14 Vincent LejeuneR600: Do not fold single instruction with more that...
2013-02-14 Michel DanzerR600: Add lit tests for texture sampling instruction...
2013-02-13 Tom StellardR600: Add support for 128-bit parameters
2013-02-07 Tom StellardR600: Add support for SET*_DX10 instructions
2013-02-07 Tom StellardR600: Add tests for unsupported condition codes.
2013-02-07 Tom StellardR600: Fix assembly name for SETGT_INT
2013-02-05 Tom StellardR600: Add tests for instruction predicates
2013-02-05 Tom StellardR600: Emit function name in the AsmPrinter
2013-01-31 Tom StellardR600: Fold clamp, neg, abs
2013-01-02 Tom StellardDAGCombiner: Avoid generating illegal vector INT_TO_FP...
2012-12-21 Tom StellardR600: Expand vec4 INT <-> FP conversions
2012-12-11 Tom StellardAdd R600 backend
2012-07-16 Tom StellardRevert "test/CodeGen/R600: Add some basic tests v6"
2012-07-16 Tom Stellardtest/CodeGen/R600: Add some basic tests v6