Revert "[LSR] Generate and use zero extends"
[oota-llvm.git] / test / MC / Disassembler / Hexagon / alu32_alu.txt
2015-06-10 Colin LeMahieu[Hexagon] Adding decoders for signed operands and ensur...
2015-01-29 Colin LeMahieu[Hexagon] Organizing tests and adding a few missing...
2015-01-29 Colin LeMahieu[Hexagon] Adding alu vector instructions
2014-12-30 Colin LeMahieu[Hexagon] Updating constant extender def, adding alu...
2014-12-09 Colin LeMahieu[Hexagon] Fixing broken tests.
2014-12-09 Colin LeMahieu[Hexagon] Updating rr/ri 32/64 transfer encodings and...
2014-12-08 Colin LeMahieu[Hexagon] Adding add/sub with saturation. Removing...
2014-12-05 Colin LeMahieu[Hexagon] Adding sub/and/or reg, imm forms
2014-12-05 Colin LeMahieu[Hexagon] Adding tfrih/l instructions.
2014-12-05 Colin LeMahieu[Hexagon] Adding add reg, imm form with encoding bits...
2014-12-05 Colin LeMahieu[Hexagon] Marking several instructions as isCodeGenOnly...
2014-12-04 Colin LeMahieu[Hexagon] Marking some instructions as CodeGenOnly...