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[Hexagon] Updating rr/ri 32/64 transfer encodings and adding tests.
[oota-llvm.git]
/
test
/
MC
/
Disassembler
/
Hexagon
/
alu32_alu.txt
2014-12-09
Colin LeMahieu
[Hexagon] Updating rr/ri 32/64 transfer encodings and...
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2014-12-08
Colin LeMahieu
[Hexagon] Adding add/sub with saturation. Removing...
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2014-12-05
Colin LeMahieu
[Hexagon] Adding sub/and/or reg, imm forms
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2014-12-05
Colin LeMahieu
[Hexagon] Adding tfrih/l instructions.
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2014-12-05
Colin LeMahieu
[Hexagon] Adding add reg, imm form with encoding bits...
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2014-12-05
Colin LeMahieu
[Hexagon] Marking several instructions as isCodeGenOnly...
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2014-12-04
Colin LeMahieu
[Hexagon] Marking some instructions as CodeGenOnly...
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