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[Hexagon] Adding add/sub with carry, logical shift left by immediate and memop instru...
[oota-llvm.git]
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test
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MC
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Disassembler
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Hexagon
/
alu32_perm.txt
2014-12-10
Colin LeMahieu
[Hexagon] Adding combine ri/ir instructions.
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2014-12-08
Colin LeMahieu
[Hexagon] Adding combine reg, reg with predicated forms.
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2014-12-08
Colin LeMahieu
[Hexagon] Adding packhl instruction.
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2014-12-05
Colin LeMahieu
[Hexagon] Updating mux_ir/ri/ii/rr with encoding bits
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2014-12-05
Colin LeMahieu
[Hexagon] Adding DoubleRegs decoder. Moving C2_mux...
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2014-12-05
Colin LeMahieu
[Hexagon] Adding combine reg-reg forms.
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2014-12-05
Colin LeMahieu
[Hexagon] Marking several instructions as isCodeGenOnly...
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