Revert "[LSR] Generate and use zero extends"
[oota-llvm.git] / test / MC / Disassembler / Hexagon / xtype_alu.txt
2015-02-03 Colin LeMahieu[Hexagon] Adding missing vector multiply instruction...
2015-01-30 Colin LeMahieu[Hexagon] Adding XTYPE/ALU vector instructions. Organi...
2015-01-28 Colin LeMahieu[Hexagon] Updating many V4 intrinsic patterns. Adding...
2015-01-05 Colin LeMahieu[Hexagon] Adding add/sub with carry, logical shift...
2015-01-05 Colin LeMahieu[Hexagon] Adding rounding reg/reg variants, accumulatin...
2015-01-05 Colin LeMahieu[Hexagon] Adding V4 logic-logic instructions and tests.
2015-01-05 Colin LeMahieu[Hexagon] Adding orand, bitsplit reg/reg, and modwrap...
2015-01-05 Colin LeMahieu[Hexagon] Adding round reg/imm and bitsplit instructions.
2014-12-31 Colin LeMahieu[Hexagon] Adding accumulating add/sub, doubleword logic...
2014-12-16 Colin LeMahieu[Hexagon] Adding asr/lsr/asl reg/imm, asl with saturati...
2014-12-16 Colin LeMahieu[Hexagon] Adding absolute value, and negate with saturation
2014-12-15 Colin LeMahieu[Hexagon] Adding logical-logical accumulation instructi...
2014-12-12 Colin LeMahieu[Hexagon] Adding double word add/min/minu/max/maxu...
2014-12-11 Colin LeMahieu[Hexagon] Adding encoding information for sign extend...
2014-12-08 Colin LeMahieu[Hexagon] Fixing broken test.
2014-12-08 Colin LeMahieu[Hexagon] Adding xtype doubleword add, sub, and, or...
2014-12-08 Colin LeMahieu[Hexagon] Adding xtype parity, min, minu, max, maxu...
2014-12-08 Colin LeMahieu[Hexagon] Adding xtype halfword add/sub ll/hl/lh/hh...