clk: rockchip: rk3228: fix gpu gate-register

Fix a typo making the aclk_gpu and aclk_gpu_noc access a wrong register to
handle its gate.

Change-Id: Ie0bac8014363af7c0409b8a56eacf2e858818843
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>

arm64: dts: rk3368-r88: gmac work up

Change-Id: I43ffe5abe8293232f026f4696b17b36024d392cd
Signed-off-by: huweiguo <hwg@rock-chips.com>

ARM: dts: rockchip: Reduce the time of phy reset for rk3288-evb

It is too long to reset the time with 1000ms, which
would make the system init and resume slowly, 50ms
is enough.

Change-Id: Ifba39f401d14e161dd3d49e1b20ae102569ebb58
Signed-off-by: David Wu <david.wu@rock-chips.com>

arm64: rockchip_linux_defconfig: enable drm tve

Change-Id: I1e3ddee6b8f0b1987604fff727d4e33ef35c7d5c
Signed-off-by: algea.cao <algea.cao@rock-chips.com>

drm/rockchip: vop: support rk3328 linux drm cvbs

Change-Id: Ie412fb30794b0addb2a4a0844af65e8356ab98c0
Signed-off-by: algea.cao <algea.cao@rock-chips.com>

drm/rockchip: support rk3328 linux drm cvbs

This adds support for Rockchip CVBS found on rk3328 Linux.
The CVBS driver is based on the DRM framework.
NTSC(720x480i60hz) and PAL(720x576i50hz) modes are supported.
it's worth noting that rk3328 CVBS dclk is base on hdmi clk,so hdmi
should be enabled.

Change-Id: I059808111bfa96724eb629b6fc37915a4852e234
Signed-off-by: algea.cao <algea.cao@rock-chips.com>

net: wireless: rockchip_wlan: add rtl8189fs support

update rtl8189fs wifi driver to version v4.3.24.8_22657.20170607

Change-Id: Ia8154d438b8d17eb334ccac0bd366f19d7b0f785
Signed-off-by: huweiguo <hwg@rock-chips.com>

Revert "usb: xhci-plat: check hcc_params after add hcd"

This reverts commit 4301c33db2829da207884f4c66bba798062db033.

Since we have merged upstream patch, so let's revert this patch.

Change-Id: I188629f566e50810bd633bff8cc63edda42efe28
Signed-off-by: William Wu <william.wu@rock-chips.com>

arm64: dts: rk3399-mid: add otg switch regulator node

Change-Id: I61cb0c65c3bec7750f6b58711e7271c42c72b8bf
Signed-off-by: Wu Liangqing <wlq@rock-chips.com>

arm64: dts: rk3368-p9: add otg switch regulator node

Change-Id: Ia200739711b6cc88e605981c325124720b1dc105
Signed-off-by: Jianhong Chen <chenjh@rock-chips.com>

power: rk818-charger: set otg5v by regulator framework

because rk818 regulator driver registers all regulators into
system without checking whether they are defined in dts, so we
have to control it by regulator framework. Otherwise,
psci_system_suspend_finish() will disable it after system wakeup.

Change-Id: Ia9d9c0b7a8cf42ccee071ac0416c1ef2f711df2f
Signed-off-by: Jianhong Chen <chenjh@rock-chips.com>

power: rk818-charger: support set charge current by battery temperature

Change-Id: I10b71fae6400f3c0125cab7af1524c2091c8924a
Signed-off-by: Jianhong Chen <chenjh@rock-chips.com>

arm64: dts: rk3368-r88: r88 board work up

Change-Id: I86b88bb57d6c61b6dfd898cc45bc927c57a6c6ec
Signed-off-by: Huang zhibao <hzb@rock-chips.com>

ARM: dts: rk3229-gva-sdk: let wifi/bt working properly

Change-Id: I548200c4e81b56cbfdaa78b86369cdb5880b1fba
Signed-off-by: Yankun Zheng <zyk@rock-chips.com>

arm: rockchip_defconfig: netfilter: add iptables for IPV6

Change-Id: I5c5709cc5335ce0ac5670df7fa0af41eab6e35dc
Signed-off-by: Xu Xuehui <xxh@rock-chips.com>

net: wireless: rockchip_wlan: fix bug for ap6335

1. fix when start softap, wifi driver crash
2. fix p2p mac addr not correct, this case p2p can not use

Change-Id: Ia9b5d7ac660ec9b954a682345c52778f7534229e
Signed-off-by: Xu Xuehui <xxh@rock-chips.com>

net: wireless: rockchip_wlan: update rtl8189es wifi driver to version v4.3.18.4_22798.20170620

Change-Id: I257bf2273e34ea9fcc5e1f4199abed892bc1c0d4
Signed-off-by: huweiguo <hwg@rock-chips.com>

FROMLIST: drm/rockchip: add fb_dmabuf_export support

Add support for fb_dmabuf_export call, which is executed when ioctl
FBIOGET_DMABUF is called.

Change-Id: I13b753ae25d043835b1f4ffc20b5e233171d1096
Signed-off-by: Guillaume Tucker <guillaume.tucker@arm.com>
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
(am from https://github.com/ARM-software/linux/commit/61062681c90f49e129c0602ebe755a12787fbd66)

FROMLIST: fb: add dma-buf support

Add support for the dma-buf exporter role to the frame buffer API. The
importer role isn't meaningful for frame buffer devices, as the frame
buffer device model doesn't allow using externally allocated memory.

taken from an RFC on the linaro-mm-sig mailing list:
http://lists.linaro.org/pipermail/linaro-mm-sig/2012-June/002167.html

Fixes by Mark Yao:
  add FBIOGET_DMABUF to compat_ioctl.

Change-Id: I39c9bbdd6b88c6d5ba7524abfc5b560dceb4633e
Signed-off-by: Guillaume Tucker <guillaume.tucker@arm.com>
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
(am from https://patchwork.linuxtv.org/patch/12980)

drm/rockchip: protect loader clocks

Change-Id: Ie9217de35ea1dc11d99b6340fc9f6ecc27ba33c8
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>

drivers: rk_nand: modify write permissions for proc files

modify "rknand" and "mtd" write permissions, read only.

Change-Id: Ib5b35059c5f075b1bade4400e1bf846222ae9a49
Signed-off-by: Zhaoyifeng <zyf@rock-chips.com>

power: rk818-charger: fix input current 80ma define error

1. input current 800ma should be 80ma, it's safe to change,
   because 800ma was not used;
2. set lowest one as default value when decode charge parameter.

Change-Id: I1683ebff708a62db2711b40f8f449f07936245f4
Signed-off-by: Jianhong Chen <chenjh@rock-chips.com>

power: rk818-battery: update ts1 current select

select 40uA when temperature lower than 0'C, otherwise 60uA.

Change-Id: Ib235441c3adb146b8d1746a435875c19b1d8624d
Signed-off-by: Jianhong Chen <chenjh@rock-chips.com>

power: rk818-battery: fix battery charging state report error

RK818_VB_MON_REG register needs at least 100ms to be correct
status for checking whether charger is online or offline.
So We search power_supply_class to get usb and ac psy for
charging state.

Change-Id: Ic332c055100309481d0dcd6d4bf030cc8db77d2d
Signed-off-by: Jianhong Chen <chenjh@rock-chips.com>

power: rk818-battery: add notify to broadcast battery temperature

Change-Id: I2ee392f1885e87b0398eaff5ab7d0a0c89527e93
Signed-off-by: Jianhong Chen <chenjh@rock-chips.com>

ARM: dts: rk322x-android: enable uart1

Change-Id: I5218cb893854900bb6a4b50910078be0cc598475
Signed-off-by: Binyuan Lan <lby@rock-chips.com>

UPSTREAM: drm/edid: Move dvi_dual/max_tmds_clock parsing out from drm_edid_to_eld()

drm_edid_to_eld() is just mean to cook up the ELD for the audio driver,
so having it parse non-audio related stuff seems just wrong, and
potentially could lead to that information not being even filled out
if the function doesn't even get called. Let's move that stuff to the
place where we parse the color formats and whatnot from the CEA ext
block.

Change-Id: I8f881f192ed06f4e16ec5e3811690c1df62c7546
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Link: http://patchwork.freedesktop.org/patch/msgid/1475070703-6435-9-git-send-email-ville.syrjala@linux.intel.com
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
(cherry picked from commit 23ebf8b9eab9151c3cccca8dbf44a8d47357158d)

UPSTREAM: drm/edid: Move dvi_dual/max_tmds_clock to drm_display_info

We have the drm_display_info for storing information about the sink, so
let's move dvi_dual and max_tmds_clock in there.

v2: Deal with superfluous code shuffling
    Document dvi_dual and max_tmds_clock too

Change-Id: I678b50021e8b9fb03554f15e2bc003037813d51a
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: "Christian König" <christian.koenig@amd.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Christian König <christian.koenig@amd.com> (v1)
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Link: http://patchwork.freedesktop.org/patch/msgid/1475070703-6435-5-git-send-email-ville.syrjala@linux.intel.com
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
(cherry picked from commit 2a272ca9b8f748aa50f5f2df391a4bf05fd9fd29)

UPSTREAM: drm/edid: Make max_tmds_clock kHz instead of MHz

We generally store clocks in kHz, so let's do that for the
HDMI max TMDS clock value as well. Less surpising.

v2: Deal with superfluous code shuffling

Change-Id: I27afd0604e5e7f1bfaa572c1c5b81ecfbcf0994e
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: "Christian König" <christian.koenig@amd.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Christian König <christian.koenig@amd.com> (v1)
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Link: http://patchwork.freedesktop.org/patch/msgid/1475070703-6435-4-git-send-email-ville.syrjala@linux.intel.com
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
(cherry picked from commit ab5603c4d334224e3a884e62e7083ec69849fa7a)

UPSTREAM: drm/edid: Clear the old cea_rev when there's no CEA extension in the new EDID

It's not a good idea to leave stale cea_rev in the drm_display_info. The
current EDID might not even have a CEA ext block in which case we'd end
up leaving the stale value in place.

Change-Id: I57e2bd4a92ddcab8c8f345c5e7e251cfa1fbd231
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Link: http://patchwork.freedesktop.org/patch/msgid/1475070703-6435-8-git-send-email-ville.syrjala@linux.intel.com
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
(cherry picked from commit 011acce2859ad50b7a923cad4a726220b5f24455)

UPSTREAM: drm/edid: Reduce the number of times we parse the CEA extension block

Instead of parsing parts of the CEA extension block in two places
to determine supported color formats and whatnot, let's just
consolidate it to one function. This also makes it possible to neatly
flatten drm_assign_hdmi_deep_color_info().

Change-Id: I68bd125757e6e5c8f13db62e52c4da827c040809
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Link: http://patchwork.freedesktop.org/patch/msgid/1475070703-6435-7-git-send-email-ville.syrjala@linux.intel.com
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
(cherry picked from commit 1cea146a806ae1f34cb1b5e3206ff63a2bb90782)

UPSTREAM: drm/edid: Don't pass around drm_display_info needlessly

We already pass the connector to drm_add_display_info() and
drm_assign_hdmi_deep_color_info(), so passing the
connector->display_info also is pointless.

Change-Id: I6c2035b7d9dd942adeb4e3477ef8999aca4a74a4
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Link: http://patchwork.freedesktop.org/patch/msgid/1475070703-6435-6-git-send-email-ville.syrjala@linux.intel.com
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
(cherry picked from commit 1826750f5775fa17909d02755bc872dfcfc6685e)

UPSTREAM: drm/edid: Clear old dvi_dual/max_tmds_clock before parsing the new EDID

Clear out old max_tmds_clock and dvi_dual information (possibly from a
previous EDID) before parsing the current EDID. Tne current EDID might
not even have these in its HDMI VSDB, which would mean that we'd leave
the old stale values in place.

Change-Id: Ia0acb9ca673f8bf9badfda1cf99899298bae464b
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Link: http://patchwork.freedesktop.org/patch/msgid/1475070703-6435-3-git-send-email-ville.syrjala@linux.intel.com
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
(cherry picked from commit 75d7e542bd3669a7ce41b713be8d3fd71e0ed2fa)

UPSTREAM: drm/edid: Clear old audio latency values before parsing the new EDID

Clear out stale audio latency information (potentially from a previous
EDID) before constructing the ELD from the EDID.

Change-Id: I1e770776f031864f597c5cd143c5fc120b313b7d
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Link: http://patchwork.freedesktop.org/patch/msgid/1475070703-6435-2-git-send-email-ville.syrjala@linux.intel.com
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
(cherry picked from commit 85c91580555ac610b266260bc7866c51bdc4d205)

UPSTREAM: drm/edid: CEA mode 64 1080p100 vsync pulse width incorrect

  In the CEA-861 specification VIC 64 specifies a vsync pulse of 5 and
a backporch of 36. Adjust vsync pulse width to match specification.

Change-Id: I8a02c2c754644e911eff74c4a179a6825398f2d7
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
Signed-off-by: Sean Paul <seanpaul@chromium.org>
Link: http://patchwork.freedesktop.org/patch/msgid/1471282288-30909-1-git-send-email-clinton.a.taylor@intel.com
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
(cherry picked from commit 8f0e4907a8e7545850ae093a0286833f3949e4cb)

UPSTREAM: drm/edid: add displayid detailed 1 timings to the modelist. (v1.1)

The tiled 5K Dell monitor appears to be hiding it's tiled mode
inside the displayid timings block, this patch parses this
blocks and adds the modes to the modelist.

v1.1: add missing __packed.

Change-Id: Ide9eb60dd88614669ea5070c9135a880819c71f0
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=95207
Signed-off-by: Dave Airlie <airlied@redhat.com>
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
(cherry picked from commit a39ed680bddb1ead592e22ed812c7e47286bfc03)

UPSTREAM: drm/edid: move displayid validation to it's own function.

We need to use this for validating modeline additions.

Change-Id: Idda40c52ff9372433e8bf81e1df5af7b59ce9b4c
Signed-off-by: Dave Airlie <airlied@redhat.com>
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
(cherry picked from commit c97291774c1b867b56c3d439ddaec9a965cf559e)

UPSTREAM: drm/displayid: Iterate over all DisplayID blocks

This will iterate over all DisplayID blocks found in the buffer.
Previously only the first block was parsed.

https://bugs.freedesktop.org/show_bug.cgi?id=95207

Change-Id: I952ea2442e8b7c31d8ca882cff8211f008cdd073
Signed-off-by: Tomas Bzatek <tomas@bzatek.net>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
(cherry picked from commit 3a4a2ea39f86c581054794c0a727597745f1084b)

UPSTREAM: drm/edid: move displayid tiled block parsing into separate function.

This just makes the code easier to follow.

Change-Id: Ic3ca12dd72c44fccfa16503822611ab4fd6b46ef
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
(cherry picked from commit 5e546cd5b3bc76824069ffa98c52a5f48cf91aba)

UPSTREAM: drm/edid: Fix parsing of EDID 1.4 Established Timings III descriptor

The EDID 1.4 specification section 3.10.3.9 defines an Established Timings III
descriptor (tag #F7h). The parsing of this descriptor by drm_est3_modes() is
off by one byte: the offset of the first timing bitmap is 6, not 5.

Change-Id: Ic24532d54245e035feb474309a609d7efb330658
Signed-off-by: Paul Parsons <lost.distance@yahoo.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/20160328002258.E75DF6E35D@gabe.freedesktop.org
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
(cherry picked from commit f3a32d74ef733e1ed1a0b804c17ec27081e0ff37)

UPSTREAM: drm/edid: Fix EDID Established Timings I and II

Three of the VESA DMT timings in edid_est_modes[] are slightly off.
1. 640x480@72Hz vsync_end should be 492, not 491.
2. 640x480@60Hz clock should be 25175, not 25200.
3. 1024x768@75Hz clock should be 78750, not 78800.
This patch corrects those timings per the VESA DMT specification, and
thus brings them into line with the identical timings in drm_dmt_modes[].

Change-Id: I351bc886ef2fb120ed62caaff9d0fff6b1868e4f
Signed-off-by: Paul Parsons <lost.distance@yahoo.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/20160402100817.B60776E23A@gabe.freedesktop.org
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
(cherry picked from commit 87707cfdc387681dc702f00dfcffc26ca0bc5f71)

UPSTREAM: drm/edid: Set 8 bpc color depth for displays with "DFP 1.x compliant TMDS".

According to E-EDID spec 1.3, table 3.9, a digital video sink with the
"DFP 1.x compliant TMDS" bit set is "signal compatible with VESA DFP 1.x
TMDS CRGB, 1 pixel / clock, up to 8 bits / color MSB aligned".

For such displays, the DFP spec 1.0, section 3.10 "EDID support" says:

"If the DFP monitor only supports EDID 1.X (1.1, 1.2, etc.)
 without extensions, the host will make the following assumptions:

 1. 24-bit MSB-aligned RGB TFT
 2. DE polarity is active high
 3. H and V syncs are active high
 4. Established CRT timings will be used
 5. Dithering will not be enabled on the host"

So if we don't know the bit depth of the display from additional
colorimetry info we should assume 8 bpc / 24 bpp by default.

This patch adds info->bpc = 8 assignement for that case.

Change-Id: Ie7603f8bf19eeeb1cd1988b6a245ead5d2e52763
Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
(cherry picked from commit 210a021dab639694600450c14b877bf3e3240adc)

UPSTREAM: drm/edid: respect connector force for drm_get_edid ddc probe

Skip DDC probe for forced connector status. Don't try to read the EDID
if the connector is forced off. Skipping probe for forced on connectors
will make more sense when drm_do_get_edid() will handle override and
firmware EDIDs.

Change-Id: I43c16b3bfd85520536445265ee693765538e4800
Suggested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1487344854-18777-4-git-send-email-jani.nikula@intel.com
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
(cherry picked from commit 15f080f08d48af9388142e45a247c8410736178b)

ARM: dts: rk3229-gva-sdk: add new dts for google voice assistant sdk.

Change-Id: Ib1fedf6a86dff770f59e1a9313356d65c39835a4
Signed-off-by: Wenping Zhang <wenping.zhang@rock-chips.com>

ARM: rockchip_defconfig: enable CONFIG_RK_NAND support.

Change-Id: If44d8809787e065cddfcbbd207a2b3ba3b97085d
Signed-off-by: Wenping Zhang <wenping.zhang@rock-chips.com>

ARM: dts: rk322x: add nandc support

Change-Id: I7a95fc186cd49fcf1c835ee0cd65eb2244caaa32
Signed-off-by: Wenping Zhang <wenping.zhang@rock-chips.com>

ARM: dts: rk3229-echo-v10: let wifi/bt working properly

Change-Id: I943f77203f4a568921a602cd06b0ab096108f553
Signed-off-by: Binyuan Lan <lby@rock-chips.com>

ARM: dts: rk322x: add another GPIO sets for UART1

Change-Id: Ibb32b7c9fb59f9adad4d4645967aa9f1c5032f5c
Signed-off-by: Binyuan Lan <lby@rock-chips.com>

ARM: dts: rk322x-android: enable HDMI display

Change-Id: I7121e735e5f113cf56cf715a73560c0f9cef69eb
Signed-off-by: WeiYong Bi <bivvy.bi@rock-chips.com>

ARM: dts: rk322x: add hdmi support

Change-Id: Idc8aded6bccb39ea2649cd846f029dbb9ceee219
Signed-off-by: WeiYong Bi <bivvy.bi@rock-chips.com>

MALI: utgard: fix deadlocks when CONFIG_SYNC is set

This is the content of
Case693349_the_spinlock_fix_patch_2_for_kernel_4.4.patch
from support_mali, with slight modifications for building
with rockchip_linux_defconfig,
in which CONFIG_SYNC is not set.

Change-Id: Icedff21f7941fd1aefceb6be4fda638378fe4ca8
Signed-off-by: chenzhen <chenzhen@rock-chips.com>

MALI: utgard: remove no longer used source files

Change-Id: I8e686736eca19cf2b7854c82fe83fc128501a221
Signed-off-by: chenzhen <chenzhen@rock-chips.com>

MALI: utgard: upgrade DDK to r7p0-00rel1

Change-Id: If789dea2b6a9c11dc82c6f91d4bdd10761e2f7d1
Signed-off-by: chenzhen <chenzhen@rock-chips.com>

phy: rockchip-inno-usb2: disable id irq in pm suspend

The otg id voltage is provided from usb2 phy power. On some
rockchip platforms (e.g. rk3399), the usb2 phy power will be
turned off when enter pm suspend, this will trigger id fall
interrupt. But current code enable the ID interrupt consistently,
it may result in the mistake of ID changing operation even if
the state of ID pin is not changed. So disable ID irq when
suspend and enable when resume.

Change-Id: Icac35f13861fd639e4b422b31182a68add73836d
Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com>

drm/rockchip: hdmi: Add support for rk3228

RK3228 uses the Synopsys DWC HDMI TX controller and the INNO HDMI PHY to
enabling the integration of a complete HDMI Transmmiter interface.

Change-Id: I90f997968fb2de4165a31216c8aee8213089eab5
Signed-off-by: WeiYong Bi <bivvy.bi@rock-chips.com>

arm: rockchip_defconfig: enable CONFIG_PHY_ROCKCHIP_INNO_HDMI_PHY

Change-Id: If93eea5cfdf28042b75da0710287ad6c768338d2
Signed-off-by: WeiYong Bi <bivvy.bi@rock-chips.com>

phy: rockchip-inno-hdmi-phy: Add Inno HDMI PHY support

INNO HDMI 2.0 TX PHY is compliant with HDMI 2.0 specification
and optimized up to 3.72Gbps per TMDS link High-Definition
applications with supporting 3D Display and up to 4Kx2K@60/50Hz
UHD resolution at 10-bit YCbCr 4:2:0 video input mode.

Change-Id: I1f8b2e5c656378188dca8e02df6d52bad2919da8
Signed-off-by: WeiYong Bi <bivvy.bi@rock-chips.com>

drm: bridge: dw-hdmi: fix panic when misc_deregister()

Change-Id: I6ab7eb4e8a756e5ae62b181e36b9bff4f6dc7ebf
Signed-off-by: xuhuicong <xhc@rock-chips.com>

drm/rockchip: hdmi: Use Synopsys HDMI TX Controller YUV420 bus format

Change-Id: Ib787054dc1b6d81090a6aa94c3dabce91219e335
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>

drm/rockchip: vop: support Synopsys HDMI TX Controller YUV420 bus_format

MEDIA_BUS_FMT_UYYVYY8_0_5X24 and MEDIA_BUS_FMT_UYYVYY10_0_5X30 are
bus_format of YUV420 data between Rockchip vop and Synopsys HDMI
TX Controller.

Change-Id: Id06e7cc7703e9b12e1a7f64cdbacc5e8a98b2b45
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>

drm: bridge: dw-hdmi: add more check for HDCP function

On RK3328, dw-hdmi HDCP driver is loaded slower than dw-hdmi.
hdmi->hdcp->hdcp_start is NULL when dw-hdmi call the hdcp_start,
cause following system crash:

Unable to handle kernel NULL pointer dereference at virtual address 00000000
pgd = ffffff8009292000
[00000000] *pgd=000000007e1fe003, *pud=000000007e1fe003, *pmd=0000000000000000
Internal error: Oops: 86000005 [#1] SMP
Modules linked in:
CPU: 0 PID: 1 Comm: swapper/0 Not tainted 4.4.70 #418
Hardware name: Rockchip RK3328 EVB (DT)
task: ffffffc0003a0000 ti: ffffffc0003a8000 task.ti: ffffffc0003a8000
PC is at 0x0
LR is at dw_hdmi_update_power+0xef4/0x1004
pc : [<0000000000000000>] lr : [<ffffff800849e778>] pstate: 60000045
sp : ffffffc0003ab3b0
x29: ffffffc0003ab3b0 x28: 000000000000410b
x27: 0000000000000000 x26: 0000000000000000
x25: ffffffc07770d028 x24: 000000000000410b
x23: 0000000000000000 x22: 0000000000000001
x21: 0000000000000002 x20: ffffff8008c02000
x19: ffffff8008c02d90 x18: 0000000062475a46
x17: 0000000000000000 x16: 000000000000000e
x15: 0000000000000007 x14: 0ffffffffffffffd
x13: 0000000000000018 x12: 0101010101010101
x11: 7f7f7f7f7f7fff7f x10: fefefefeff01f305
x9 : ff7fff7f7f7f7f7f x8 : ffffff80091db5df
x7 : 0000000000000000 x6 : 0000000000000004
x5 : 0000000000000015 x4 : 0000000000140b82
x3 : 000000000106b1af x2 : 0000000000000001
x1 : 0000000000000000 x0 : ffffffc076e25e00

Change-Id: I0fccf9d8e06f7acdb56d8e5360acf0df026fee10
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>

UPSTREAM: drm: bridge: dw-hdmi: fix input format/encoding from plat_data

The plat_data->input_bus_format and plat_data->input_bus_encoding
are unsigned long and are always >=0, but the value 0 was still
considered as RGB888 for input_bus_format and default color space
for input_bus_encoding in the reworked code.

This patch changes the if statement check for a non-zero value to
either use the default input bus_format and/or bus_encoding for a zero
value and the provided bus_format and/or bus_encoding for a
non zero value.

Thanks to Dan Carpenter for his bug report at [1].

Tested on Amlogic P230 (with CSC enabled for YUV444 to RGB) and Rockchip
RK3288 ACT8846 EVB Board (no CSC involved, direct RGB passthrough).

[1] http://lkml.kernel.org/r/20170406052120.GA26578@mwanda

Cc: Dan Carpenter <dan.carpenter@oracle.com>
Fixes: def23aa7e982 ("drm: bridge: dw-hdmi: Switch to V4L bus format and encodings")
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Archit Taneja <architt@codeaurora.org>
[narmstrong@baylibre.com: reworded commit message and added Fixes tag]
Link: http://patchwork.freedesktop.org/patch/msgid/1491471244-24989-1-git-send-email-narmstrong@baylibre.com
Change-Id: I1b6c08e3fe468c01fcd721fe4b4d6ec95c73528b
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
(cherry picked from commit e20c29aa722a90f3b8092b340362eabe488dbfc4)

UPSTREAM: drm: bridge: dw-hdmi: Switch to V4L bus format and encodings

Switch code to use the newly introduced V4L bus formats IDs instead of custom
defines. Also use the V4L encoding defines.

Some display pipelines can only provide non-RBG input pixels to the HDMI TX
Controller, this patch takes the pixel format from the plat_data if provided.

Change-Id: I2b70ed0f3cab8c6873bb407977738677375b24b0
Reviewed-by: Jose Abreu <joabreu@synopsys.com>
Reviewed-by: Archit Taneja <architt@codeaurora.org>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
(cherry picked from commit def23aa7e9821a3dfe3fb7b139dd0229a89fdeb0)

UPSTREAM: media: uapi: Add RGB and YUV bus formats for Synopsys HDMI TX Controller

In order to describe the RGB and YUV bus formats used to feed the
Synopsys DesignWare HDMI TX Controller, add missing formats to the
list of Bus Formats.

Documentation for these formats is added in a separate patch.

Change-Id: Ic2cab2bbe6caed5e5b6e86c60a58f26046d259be
Reviewed-by: Archit Taneja <architt@codeaurora.org>
Reviewed-by: Jose Abreu <joabreu@synopsys.com>
Acked-by: Hans Verkuil <hans.verkuil@cisco.com>
Acked-by: Mauro Carvalho Chehab <mchehab@s-opensource.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Sean Paul <seanpaul@chromium.org>
Link: http://patchwork.freedesktop.org/patch/msgid/1491230558-10804-3-git-send-email-narmstrong@baylibre.com
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
(cherry picked from commit d0353118fd589c127875290017c7fdd266937bee)

drm/rockchip: vop: initital crtc pll status

If the crtc pll status is not init, always cause mode_changed
at first dclk source generate, that would cause logo flush
fixup(10a90aa drm/rockchip: support setting specail pll for hdmi)

Change-Id: I0ee20fd098654ff89f268be82b50d2d5b605e9d5
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>

drivers: rk_nand: update ftl to support slc nand and micron L04A

1. support 128MB and 256MB slc nand flash
2. support micron L04A 3D mlc nand flash
3. fix 3036 read sn fail issue

Change-Id: If08b3f8bd37c9d9c161b733f6127b137a8bfdd4f
Signed-off-by: Zhaoyifeng <zyf@rock-chips.com>

soc: rockchip: Add dummy rockchip_pm_register_notify_to_dmc

build fix for CONFIG_ROCKCHIP_PM_DOMAINS=n

Change-Id: Iffa0bfa3ab7fc78360341f188f645d2579edde2e
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>

camera: rockchip: camsys driver v0.0x22.1

gpio0_D is unavailable on rk3288 with current pinctrl driver.

Change-Id: I7d38ebd3b00ac0df31861406f758bdd9e57f9903
Signed-off-by: xcq <shawn.xu@rock-chips.com>

Revert "pinctrl: rockchip: Add rk3288 GPIO0_D0 ~ GPIO0_D7 pins support"

This reverts commit 1d9964a98931ac8f8680664e2a0731ecffc3448b.

Double confirmation, GPIO0_D0 ~ GPIO0_D7 pins are not connected to pad,
this is a wrong commit, revert this commit.

Change-Id: Iebec11ee47a68fe51ec90361fd412d05df832998
Signed-off-by: David Wu <david.wu@rock-chips.com>

power_supply: add cw2015 battery support

Change-Id: I36d65b9765a3303169f0ff60025d9ae722ceb1a9
Signed-off-by: Shunqing Chen <csq@rock-chips.com>

drm: bridge: dw-hdmi: add hdcp1.4 support

First, write hdcp key by "ProvisioningTool" if you want to
enable hdcp function, or else will auth fail.

To check whether the hdcp is enable or not
  #cat /sys/class/misc/hdmi_hdcp1x/enable
  0:hdcp is disabled
  1:hdcp is enabled, hdmi screen will be pink if it is failed;
  2:hdcp is enabled, hdmi screen will be normal if it is failed;

Enable or disable hdcp function
  #echo 0 > /sys/class/misc/hdmi_hdcp1x/enable
  #echo 1 > /sys/class/misc/hdmi_hdcp1x/enable
  #echo 2 > /sys/class/misc/hdmi_hdcp1x/enable

Get the status of hdcp
  #cat /sys/class/misc/hdmi_hdcp1x/status
  The result will be one of the follow list:
    hdcp disable;
    hdcp_auth_start
    hdcp_auth_success;
    hdcp_auth_fail;
    unknown status.

Change-Id: Iac6c7d6a1196ce9cf2869d7916bbe6c8941ec13b
Signed-off-by: xuhuicong <xhc@rock-chips.com>

clk: rockchip: rk3228: add SCLK_SDIO_SRC clk id

This patch exports sdio src clock for dts reference.

Change-Id: I3e83cce4da3d82af4b18df43ecd51c504d308c02
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

drm/rockchip: gem: don't limit to 32bit mapping when not support LPAE

Change-Id: I3d2b41cfb0be3122ccb291802feb950017acdf44
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>

drm/rockchip: hdmi: correct 3328 hdmi phy power up timing

According to spec, TMDS driver should power up between PLL
power up and PLL lock.

There is an mistake of pdata en register, the real register
is reg2 bit0, not reg1 bit0.

Change-Id: I9d2b707cbcfd70b63f4a1a277a85f21b62643d2e
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>

drm/rockchip: logo: restore display if show logo failed

Change-Id: I554eaff439b6cd13770fb81ec5c9df6693e17f29
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>

dmaengine: pl330: _loop_cyclic supports unaligned size

Change-Id: If724fb0c414edc13bba94def8da78c28a4cec69a
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>

drm/rockchip: vop: correct clk_set_parent return value check

Change-Id: I3da501169739759426c83a3b7e6e255c717e226c
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>

drm/rockchip: vop: get rid of max_output.height check

Actually vop hardware has no output height limit, so no
need limit display with max_output.height

Change-Id: Ide70cb28af9a23c1a12c068168b13aac37041b28
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>

ARM64: dts: rk3328-evb: set hdmi ddc clock rate to 50KHz

Change-Id: I59bc54a17d697e742a3753baba692f3541f742e4
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>

driver: mpu: to support mpu6881/mpu6880

Change-Id: I731788cd35d27d2aab946ccb22f744aad85f7be3
Signed-off-by: Zorro Liu <lyx@rock-chips.com>

ARM64: dts: rk3368-p9: set sleep mode config RKPM_SLP_ARMOFF

Change-Id: I65b87a37f029e316cf048bf7da790d51a046cca2
Signed-off-by: Zorro Liu <lyx@rock-chips.com>

ARM64: dts: rockchip: enable rockchip_suspend node of rk3368-p9 and rk3368-sheep board

Change-Id: Iff11ec889c372f279cf638ff2f3f2b72824abd4c
Signed-off-by: Zorro Liu <lyx@rock-chips.com>

arm64: dts: rockchip: enable dp for rk3399 evb rev3 board

Change-Id: I91043fd5caa8a639844658cc0410372785b1c43d
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>

arm64: dts: rockchip: rk3399: add dclk pll sources

Change-Id: I0e29d67d5e3738b18a7407a049d216f8dcebb8e8
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>

Documentation: dt-bindings: rockchip: introduce dclk_source

Change-Id: Iee4d40ede334f418fd4edb51319b5e03f25467c0
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>

Documentation: dt-bindings: rockchip: introduce display plls

Change-Id: Ifa7129bc5dd625c7f78040b0d506930be24c5aa0
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>

drm/rockchip: support setting specail pll for hdmi

In order to get lower jitter clock for hdmi tmds, Hardware
design that: direct get tmds clock from vpll, bypass vop.

This design can make hdmi good works, but also limit hdmi's
clock source, the vop which hdmi use need also assign to vpll,
and use same clock rate, it's hardware limitation.

This patch add a mechanism to select dclk's parent pll, then
can allocate correct pll for hdmi.

Change-Id: I9e3b4b6d3756c409782df0605706be4203d69a32
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
Suggested-by: Heiko Stuebner <heiko@sntech.de>

driver: sensor: ak09911: to match hal code, compatible with ak8963

Change-Id: Ia5768a4466512063948c48c2139356522a4557ac
Signed-off-by: Zorro Liu <lyx@rock-chips.com>

dmaengine: pl330: redefine the cyclic transfer

dmaengine_prep_dma_cyclic, to use buf_addr with size buf_len,
generate an interrupt every period_len. But DMA must restart
every period_len, it may be blocked. If i2s use it, it may
cause sound break. Infiniteloop is helpful to solve this
issue. In infiniteloop mode, when DMA transfers all buf_len
data, it goes back to the start of buf_addr and continue to
transfer endless.

Change-Id: Ibbc92c416d0a9dd58633e7991176c86300c3da98
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>

arm64: dts: rockchip: config dr_mode as otg for usb on rk3328-evb

Because we have supported to force otg mode for rk3328 in the commit
2b9b897141f1 ("phy: rockchip-inno-usb2: support to force otg mode"),
so let's config dr_mode as otg for usb otg port, and then user can
use otg peripheral mode and host mode as needed.

Change-Id: I6f55fb2aad1b8c49498af829475a8b59215251e5
Signed-off-by: William Wu <william.wu@rock-chips.com>

arm: dts: rk322x-android: add otg vbus gpio for usb2 phy0

This patch adds otg vbus gpio for usb2 phy0, and then we
can control otg vbus for otg host mode.

Change-Id: I685060270f9cb0963931a84035cad7286d99a469
Signed-off-by: William Wu <william.wu@rock-chips.com>

phy: rockchip-inno-usb2: support to force otg mode

This patch creates an usb2 phy attribute group and
provides an attribute "otg_mode" for otg port to
force otg mode independently of the voltage of otg
id pin.

In order to implement the force mode function, we can
select otg plug indicator output (AKA iddig) from GRF,
and set GRF USB otg plug indicator to "0" or "1" to
control iddig status.

We only support rk322x/rk3328 to force otg mode for
the time being.

And we need to disable usb auto suspend function if
we want to force otg mode. Add 'usbcore.autosuspend=-1'
in cmdline to disable usb auto suspend.

Usage:
[1] Force host mode
    echo host > /sys/devices/platform/<u2phy dev name>/mode

[2] Force peripheral mode
    echo peripheral > /sys/devices/platform/<u2phy dev name>/mode

[3] Force otg mode
    echo otg > /sys/devices/platform/<u2phy dev name>/mode

Legacy Usage:
[1] Force host mode
    echo 1 > /sys/devices/platform/<u2phy dev name>/mode

[2] Force peripheral mode
    echo 2 > /sys/devices/platform/<u2phy dev name>/mode

[3] Force otg mode
    echo 0 > /sys/devices/platform/<u2phy dev name>/mode

Change-Id: I875b60b0390e3bd9af34b740cba8f5d53e1df752
Signed-off-by: William Wu <william.wu@rock-chips.com>

dt-bindings: display: screen-timing: add physical size for h546dlb01

Change-Id: I51ba6c2bdacddbc16dbf79df1f36ef6f09340989
Signed-off-by: WeiYong Bi <bivvy.bi@rock-chips.com>

phy: rockchip-inno-usb2: fix possibe deadlock

The commit 611ec35fa148 ("phy: rockchip-inno-usb2: fix some
race conditions") use mutex lock to protect charger detect
work, but it will cause the following possible deadlock.

[ INFO: possible circular locking dependency detected ]
4.4.66 #563 Not tainted
-------------------------------------------------------
kworker/3:1/145 is trying to acquire lock:
(&rport->mutex){+.+...}, at: [<ffffff80083f286c>] rockchip_chg_detect_work+0x6c/0x3d0

but task is already holding lock:
((&(&rport->chg_work)->work)){+.+...}, at: [<ffffff80080be6e4>] process_one_work+0x1c4/0x6ac

which lock already depends on the new lock.
the existing dependency chain (in reverse order) is:

-> #1 ((&(&rport->chg_work)->work)){+.+...}:
[<ffffff80080fda40>] __lock_acquire+0x15c0/0x195c
[<ffffff80080fe5e8>] lock_acquire+0x190/0x250
[<ffffff80080bf534>] flush_work+0x4c/0x274
[<ffffff80080bf944>] __cancel_work_timer+0x130/0x1c0
[<ffffff80080bf9fc>] cancel_delayed_work_sync+0x10/0x18
[<ffffff80083f17a8>] rockchip_usb2phy_exit+0x54/0x6c
[<ffffff80083f07ac>] phy_exit+0x64/0xb4
[<ffffff8008772810>] dwc3_core_exit+0x44/0x98
[<ffffff80087728b0>] dwc3_suspend_common+0x4c/0x5c
[<ffffff8008772a68>] dwc3_runtime_suspend+0x38/0x5c
[<ffffff8008571784>] pm_generic_runtime_suspend+0x28/0x38
[<ffffff8008573464>] __rpm_callback+0x40/0x74
[<ffffff80085734f4>] rpm_callback+0x5c/0x80
[<ffffff8008573bc4>] rpm_suspend+0x31c/0x688
[<ffffff80085751ec>] __pm_runtime_suspend+0x58/0xa4
[<ffffff800877efc0>] dwc3_rockchip_probe+0x3f8/0x574
[<ffffff800856bcd0>] platform_drv_probe+0x58/0xa4
[<ffffff8008569bb0>] driver_probe_device+0x118/0x2b0
[<ffffff8008569e9c>] __device_attach_driver+0x88/0x98
[<ffffff8008567f4c>] bus_for_each_drv+0x7c/0xac
[<ffffff80085699e4>] __device_attach+0xa8/0x128
[<ffffff800856a00c>] device_initial_probe+0x10/0x18
[<ffffff8008569000>] bus_probe_device+0x2c/0x90
[<ffffff800856948c>] deferred_probe_work_func+0x78/0xa8
[<ffffff80080be858>] process_one_work+0x338/0x6ac
[<ffffff80080bfd54>] worker_thread+0x300/0x428
[<ffffff80080c5758>] kthread+0x104/0x10c
[<ffffff8008083080>] ret_from_fork+0x10/0x50

-> #0 (&rport->mutex){+.+...}:
[<ffffff80080faacc>] print_circular_bug+0x64/0x2c4
[<ffffff80080fd70c>] __lock_acquire+0x128c/0x195c
[<ffffff80080fe5e8>] lock_acquire+0x190/0x250
[<ffffff8008c67ac0>] mutex_lock_nested+0x80/0x3d0
[<ffffff80083f286c>] rockchip_chg_detect_work+0x6c/0x3d0
[<ffffff80080be858>] process_one_work+0x338/0x6ac
[<ffffff80080bfd54>] worker_thread+0x300/0x428
[<ffffff80080c5758>] kthread+0x104/0x10c
[<ffffff8008083080>] ret_from_fork+0x10/0x50

other info that might help us debug this:

Possible unsafe locking scenario:

        CPU0                    CPU1
        ----                    ----
   lock((&(&rport->chg_work)->work));
                                lock(&rport->mutex);
                                lock((&(&rport->chg_work)->work));
   lock(&rport->mutex);

  *** DEADLOCK ***

2 locks held by kworker/3:1/145:

stack backtrace:
CPU: 3 PID: 145 Comm: kworker/3:1 Not tainted 4.4.66 #563
Hardware name: Rockchip RK3399 Evaluation Board v3 (Android) (DT)
Workqueue: events rockchip_chg_detect_work
Call trace:
[<ffffff800808a814>] dump_backtrace+0x0/0x1c8
[<ffffff800808a9f0>] show_stack+0x14/0x1c
[<ffffff80083c1fa0>] dump_stack+0xb0/0xec
[<ffffff80080fad10>] print_circular_bug+0x2a8/0x2c4
[<ffffff80080fd70c>] __lock_acquire+0x128c/0x195c
[<ffffff80080fe5e8>] lock_acquire+0x190/0x250
[<ffffff8008c67ac0>] mutex_lock_nested+0x80/0x3d0
[<ffffff80083f286c>] rockchip_chg_detect_work+0x6c/0x3d0
[<ffffff80080be858>] process_one_work+0x338/0x6ac
[<ffffff80080bfd54>] worker_thread+0x300/0x428
[<ffffff80080c5758>] kthread+0x104/0x10c
[<ffffff8008083080>] ret_from_fork+0x10/0x50

Change-Id: I4289afb05d334bf79000090f9071cf428817a583
Signed-off-by: William Wu <william.wu@rock-chips.com>

arm64: rockchip_linux_defconfig: enable MPP_SERVICE

Change-Id: I12cb15a44e31f768bac960e3a5e6b9371d221ed3
Signed-off-by: Hans Yang <yhx@rock-chips.com>

drm/rockchip: limit gem buffer to 32bit mapping

Change-Id: I64537668aa10a2e26bdd19ac79bc417aa6c4a437
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>

drm: support loader protect for panel

Change-Id: Ie9330e3380a4925a4b7603e7206f1e0d186d2156
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>

ARM64: dts: rk3328-evb: enable vepu & h265e default

Change-Id: I94685dbeea3ceffa106593ff597f50404f58f34a
Signed-off-by: Jung Zhao <jung.zhao@rock-chips.com>

ARM64: dts: rk3328: add vepu & h265e dts node

Change-Id: I2990ac7e43d4b2d2efbf5e9cf3abe124e8767648
Signed-off-by: Jung Zhao <jung.zhao@rock-chips.com>

driver: video: rockchip: add new driver of vpu

this driver only support h264e & h265e. if you want to
enable the driver, you must modify the menuconfig and
turn on MPP_SERVICE & MPP_DEVICE.

Change-Id: I7f1c6e473eaf7aedb4fa86791412b5fbcb2c531d
Signed-off-by: buluess.li <buluess.li@rock-chips.com>
Signed-off-by: Jung Zhao <jung.zhao@rock-chips.com>