Fix Neon intrinsic immediate range checking for some double-register operands.
Some quad-register intrinsics with lane operands only take a double-register
operand for the vector containing the lane.  The valid range of lane numbers
is then half as big as you would expect from the quad-register type.
Note: This currently has no effect because those intrinsics are now handled
entirely in the header file using __builtin_shufflevector, which does its own
range checking, but I want to use this for generating tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121867 91177308-0d34-0410-b5e6-96231b3b80d8

Move Sub simplifications and additional Add simplifications out of
instcombine and into InstructionSimplify.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121861 91177308-0d34-0410-b5e6-96231b3b80d8

If we detect that the instruction we are simplifying is unreachable, arrange for
it to be replaced by undef rather than not replaced at all, the idea being that
this may reduce the amount of work done by whoever called InstructionSimplify.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121860 91177308-0d34-0410-b5e6-96231b3b80d8

Teach jump threading to "look through" a select when the branch direction of a terminator depends on it.
When it sees a promising select it now tries to figure out whether the condition of the select is known in any of the predecessors and if so it maps the operands appropriately.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121859 91177308-0d34-0410-b5e6-96231b3b80d8

Add fixups for Thumb LDR/STR instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121858 91177308-0d34-0410-b5e6-96231b3b80d8

Relax alignment fragments.

With this we don't need the EffectiveSize field anymore. Without that field
LayoutFragment only updates offsets and we don't need to invalidate the
current fragment when it is relaxed (only the ones following it).

This is also a very small improvement in the accuracy of the layout info as
we now use the after relaxation size immediately.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121857 91177308-0d34-0410-b5e6-96231b3b80d8

Patch by David Meyer to avoid a O(N^2) behaviour when relaxing fragments.

Since we now don't update addresses so early, we might relax a bit more than
we need to. This is simillar to the issue in PR8467.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121856 91177308-0d34-0410-b5e6-96231b3b80d8

add another overflow idiom

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121854 91177308-0d34-0410-b5e6-96231b3b80d8

add a note about overflow idiom recognition.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121853 91177308-0d34-0410-b5e6-96231b3b80d8

Generalize an assert.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121851 91177308-0d34-0410-b5e6-96231b3b80d8

add a shift/imul missed optimization

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121850 91177308-0d34-0410-b5e6-96231b3b80d8

add a note about a SPEC hack that gcc mainline does.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121849 91177308-0d34-0410-b5e6-96231b3b80d8

take care of some todos, transforming [us]mul_lohi into
a wider mul if the wider mul is legal.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121848 91177308-0d34-0410-b5e6-96231b3b80d8

merge two tests

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121847 91177308-0d34-0410-b5e6-96231b3b80d8

when transforming a MULHS into a wider MUL, there is no need to SRA the
result, the top bits are truncated off anyway, just use SRL.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121846 91177308-0d34-0410-b5e6-96231b3b80d8

make qsort predicate more conformant by returning 0 for equal values.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121838 91177308-0d34-0410-b5e6-96231b3b80d8

various cleanups to tblgen, patch by Garrison Venn!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121837 91177308-0d34-0410-b5e6-96231b3b80d8

Add mention that we support FreeBSD/amd64.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121832 91177308-0d34-0410-b5e6-96231b3b80d8

Add some more MC tests for ARM arithmetic instructions that update or don't
update the condition codes.  These come from my test generator and are just
the ones that MC currently assembles correctly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121830 91177308-0d34-0410-b5e6-96231b3b80d8

Copy-pastos.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121829 91177308-0d34-0410-b5e6-96231b3b80d8

Remove ConvertToMAttrImpl, it became too '-march'-specific.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121828 91177308-0d34-0410-b5e6-96231b3b80d8

llvmc: Support -march arguments that should be forwarded to llc as -mcpu.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121827 91177308-0d34-0410-b5e6-96231b3b80d8

llvmc: Better -mfpu/-mcpu support for ARM & PPC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121826 91177308-0d34-0410-b5e6-96231b3b80d8

llvmc: more complete -march table for ARM.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121825 91177308-0d34-0410-b5e6-96231b3b80d8

llvmc: Support -mabi/-mfloat-abi.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121824 91177308-0d34-0410-b5e6-96231b3b80d8

llvmc: Forward -march/-mcpu/-mtune to as & ld.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121823 91177308-0d34-0410-b5e6-96231b3b80d8

llvmc: make switch options ZeroOrMore by default.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121822 91177308-0d34-0410-b5e6-96231b3b80d8

Reapply r121808 now that the missing patterns have been supplied.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121820 91177308-0d34-0410-b5e6-96231b3b80d8

Add some missing patterns now that tLDRB and tLDRH are split into reg and
immediate versions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121819 91177308-0d34-0410-b5e6-96231b3b80d8

Fix PR8790, another instance where unreachable code can cause instruction simplification to fail,
this case involve a select that simplifies to itself.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121817 91177308-0d34-0410-b5e6-96231b3b80d8

Cleanup trailing whitespace.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121816 91177308-0d34-0410-b5e6-96231b3b80d8

Revert r121808 until I can fix the build.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121815 91177308-0d34-0410-b5e6-96231b3b80d8

thumb adr fixup needs alignment just like the t2 version.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121812 91177308-0d34-0410-b5e6-96231b3b80d8

Comments and cleaning.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121809 91177308-0d34-0410-b5e6-96231b3b80d8

Make the ISel selections for LDR/STR the same as before the LDRr/LDRi split. In
particular, we want

   ldr r2, [r3]

to be equivalent to

   ldr r2, [r3, #0]

and not

   ldr r2, [r3, r0]

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121808 91177308-0d34-0410-b5e6-96231b3b80d8

Simplify RegAllocGreedy's use of register aliases.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121807 91177308-0d34-0410-b5e6-96231b3b80d8

Simplify CCState's use of register aliases.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121806 91177308-0d34-0410-b5e6-96231b3b80d8

Simplify AggressiveAntiDepBreaker's use of register aliases.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121805 91177308-0d34-0410-b5e6-96231b3b80d8

Simplyfy RegAllocBasic by using getOverlaps instead of getAliasSet.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121801 91177308-0d34-0410-b5e6-96231b3b80d8

Introduce TargetRegisterInfo::getOverlaps(Reg), returning a list of all
registers that alias Reg, including itself. This is almost the same as the
existing getAliasSet() method, except for the inclusion of Reg.

The name matches the reflexive TRI::regsOverlap(x, y) relation.

It is very common to do stuff to a register and all its aliases:

  stuff(Reg)
  for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias)
    stuff(*Alias);

That can now be written as the simpler:

  for (const unsigned *Alias = TRI->getOverlaps(Reg); *Alias; ++Alias)
    stuff(*Alias);

This change requires a bit more constant space for the alias lists because Reg
is included and because the empty alias list cannot be shared any longer.

If the getAliasSet method is eventually removed, this space can be reclaimed by
sharing overlap lists. For instance, %rax and %eax have identical overlap sets.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121800 91177308-0d34-0410-b5e6-96231b3b80d8

Add support for MC-ized encoding of tLEApcrel and tLEApcrelJT. rdar://8755755

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121798 91177308-0d34-0410-b5e6-96231b3b80d8

Fix comment.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121797 91177308-0d34-0410-b5e6-96231b3b80d8

Multiclassify the LDR/STR encoding patterns. The only functionality difference
is the addition of the FoldableAsLoad & Rematerializable flags to some of the
load instructions. ARM has these flags set for them.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121794 91177308-0d34-0410-b5e6-96231b3b80d8

Fix a minor bug in two-address pass. It was missing a commute opportunity.
regB = move RCX
regA = op regB, regC
RAX  = move regA
where both regB and regC are killed. If regB is constrainted to non-compatible
physical registers but regC is not constrainted at all, then it's better to
commute the instruction.
       movl    %edi, %eax
       shlq    $32, %rcx
       leaq    (%rcx,%rax), %rax
=>
       movl    %edi, %eax
       shlq    $32, %rcx
       orq     %rcx, %rax
rdar://8762995

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121793 91177308-0d34-0410-b5e6-96231b3b80d8

trailing whitespace

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121792 91177308-0d34-0410-b5e6-96231b3b80d8

Move debugging code entirely within DEBUG(). Silences an unused variable
warning in the opt build.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121791 91177308-0d34-0410-b5e6-96231b3b80d8

Refactor a bit for legibility.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121790 91177308-0d34-0410-b5e6-96231b3b80d8

trailing whitespace.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121789 91177308-0d34-0410-b5e6-96231b3b80d8

Make sure to propagate the predicate operands for LEApcrel to ADR.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121788 91177308-0d34-0410-b5e6-96231b3b80d8

Fix a small bug (typo?) in the fixup for Thumb1 CBZ/CBNZ instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121784 91177308-0d34-0410-b5e6-96231b3b80d8

Add LiveIntervalUnion print methods, RegAllocGreedy::trySplit debug spew.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121783 91177308-0d34-0410-b5e6-96231b3b80d8

Use TRI::printReg instead of AbstractRegisterDescription when printing
LiveIntervalUnions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121781 91177308-0d34-0410-b5e6-96231b3b80d8

Add TargetRegisterInfo::printReg() to pretty-print registers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121780 91177308-0d34-0410-b5e6-96231b3b80d8

ARM Fixups relative to thumb functions need to have the low bit of the value
set for interworking to work properly. rdar://8755956

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121778 91177308-0d34-0410-b5e6-96231b3b80d8

Q.seenAllInterferences() must be called after Q.collectInterferingVRegs().

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121774 91177308-0d34-0410-b5e6-96231b3b80d8

MC/ARM: Fix-up fixup offset for fixup_arm_branch target specific fixup.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121772 91177308-0d34-0410-b5e6-96231b3b80d8

Trailing whitespace

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121769 91177308-0d34-0410-b5e6-96231b3b80d8

Use the integer scheduling intrinsic for integer loads and stores.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121765 91177308-0d34-0410-b5e6-96231b3b80d8

 - Insert new instructions before DomBlock's terminator,
   which is simpler than finding a place to insert in BB.
 - Don't perform the 'if condition hoisting' xform on certain
   i1 PHIs, as it interferes with switch formation.

This re-fixes "example 7", without breaking the world hopefully.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121764 91177308-0d34-0410-b5e6-96231b3b80d8

fix two significant issues with FoldTwoEntryPHINode:

first, it can kick in on blocks whose conditions have been
folded to a constant, even though one of the edges will be
trivially folded.

second, it doesn't clean up the "if diamond" that it just
eliminated away.  This is a problem because other simplifycfg
xforms kick in depending on the order of block visitation,
causing pointless work.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121762 91177308-0d34-0410-b5e6-96231b3b80d8

remove the instsimplify logic I added in r121754.  It is apparently
breaking the selfhost builds, though I can't fathom how.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121761 91177308-0d34-0410-b5e6-96231b3b80d8

clean up logic, convert std::set to SmallPtrSet, handle the case
when all 2-entry phis are simplified away.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121760 91177308-0d34-0410-b5e6-96231b3b80d8

tidy up a bit, move DEBUG down to when we commit to doing the transform so we
don't print it unless the xform happens.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121758 91177308-0d34-0410-b5e6-96231b3b80d8

use SimplifyInstruction instead of reimplementing part of it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121757 91177308-0d34-0410-b5e6-96231b3b80d8

simplify GetIfCondition by using getSinglePredecessor.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121756 91177308-0d34-0410-b5e6-96231b3b80d8

use AddPredecessorToBlock in 3 places instead of a manual loop.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121755 91177308-0d34-0410-b5e6-96231b3b80d8

make FoldTwoEntryPHINode use instsimplify a bit, make
GetIfCondition faster by avoiding pred_iterator.  No
really interesting change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121754 91177308-0d34-0410-b5e6-96231b3b80d8

remove the dead (and terrible) llvm::RemoveSuccessor function.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121753 91177308-0d34-0410-b5e6-96231b3b80d8

improve DEBUG's a bit, switch to eraseFromParent() to simplify
code a bit, switch from constant folding to instsimplify.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121751 91177308-0d34-0410-b5e6-96231b3b80d8

fix yet anohter broken line

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121750 91177308-0d34-0410-b5e6-96231b3b80d8

reapply my recent change that disables a piece of the switch formation
work, but fixes 400.perlbmk.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121749 91177308-0d34-0410-b5e6-96231b3b80d8

The tLDR et al instructions were emitting either a reg/reg or reg/imm
instruction based on the t_addrmode_s# mode and what it returned. There is some
obvious badness to this. In particular, it's hard to do MC-encoding when the
instruction may change out from underneath you after the t_addrmode_s# variable
is finally resolved.

The solution is to revert a long-ago change that merged the reg/reg and reg/imm
versions. There is the addition of several new addressing modes. They no longer
have extraneous operands associated with them. I.e., if it's reg/reg we don't
have to have a dummy zero immediate tacked on to the SDNode.

There are some obvious cleanups here, which will happen shortly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121747 91177308-0d34-0410-b5e6-96231b3b80d8

bfi A, (and B, C1), C2) -> bfi A, B, C2 iff C1 & C2 == C1. rdar://8458663

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121746 91177308-0d34-0410-b5e6-96231b3b80d8

fix fixme case typo :-)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121743 91177308-0d34-0410-b5e6-96231b3b80d8

Remove unused vector.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121741 91177308-0d34-0410-b5e6-96231b3b80d8

Add IntervalMap to the Programmer's Manual.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121740 91177308-0d34-0410-b5e6-96231b3b80d8

Remove debugging code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121738 91177308-0d34-0410-b5e6-96231b3b80d8

Try reassigning all virtual register interferences, not just those with lower
spill weight. Filter out fixed registers instead.

Add support for reassigning an interference that was assigned to an alias.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121737 91177308-0d34-0410-b5e6-96231b3b80d8

Add stub for RAGreedy::trySplit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121736 91177308-0d34-0410-b5e6-96231b3b80d8

Second attempt at make Thumb2 LEAs pseudos.  This time, perform the lowering much later, which makes the entire
process cleaner.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121735 91177308-0d34-0410-b5e6-96231b3b80d8

Fix recent buildbot breakage by pulling SimplifyCFG back to its state as of r121694, the most recent state
where I'm confident there were no crashes or miscompilations.  XFAIL the test added since then for now.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121733 91177308-0d34-0410-b5e6-96231b3b80d8

First cut of ARM/MC/ELF PIC relocations.
Test has fixme, to move to .s -> .o test when AsmParser works better.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121732 91177308-0d34-0410-b5e6-96231b3b80d8

Remove the rest of the *_sfp Neon instruction patterns.
Use the same COPY_TO_REGCLASS approach as for the 2-register *_sfp instructions.
This change made a big difference in the code generated for the
CodeGen/Thumb2/cross-rc-coalescing-2.ll test: The coalescer is still doing
a fine job, but some instructions that were previously moved outside the loop
are not moved now.  It's using fewer VFP registers now, which is generally
a good thing, so I think the estimates for register pressure changed and that
affected the LICM behavior.  Since that isn't obviously wrong, I've just
changed the test file.  This completes the work for Radar 8711675.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121730 91177308-0d34-0410-b5e6-96231b3b80d8

Simplify N2VSPat, removing some unnecessary type arguments.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121729 91177308-0d34-0410-b5e6-96231b3b80d8

temporarily disable part of my previous patch, which causes an iterator invalidation issue, causing a crash on some versions of perlbmk.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121728 91177308-0d34-0410-b5e6-96231b3b80d8

Update a comment.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121727 91177308-0d34-0410-b5e6-96231b3b80d8

Revert r121721, which broke buildbots.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121726 91177308-0d34-0410-b5e6-96231b3b80d8

Reapply r121520, PartialAlias implementation for BasicAA, now that
memdep is updated to handle it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121725 91177308-0d34-0410-b5e6-96231b3b80d8

Update memdep to handle PartialAlias as MayAlias.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121723 91177308-0d34-0410-b5e6-96231b3b80d8

Make Thumb2 LEA-like instruction into pseudos, which map down to ADR.  Provide correct fixups for Thumb2 ADR,
which is _of course_ different from ARM ADR fixups, or any other Thumb2 fixup.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121721 91177308-0d34-0410-b5e6-96231b3b80d8

Delete a line that I forgot to revert previously.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121719 91177308-0d34-0410-b5e6-96231b3b80d8

Use COPY_TO_REGCLASS instead of pseudo instructions for Neon FP patterns.
Jakob Olesen suggested that we can avoid the need for separate pseudo
instructions here by using COPY_TO_REGCLASS in the patterns.  The pattern
gets pretty ugly but it seems to work well.  Partial fix for Radar 8711675.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121718 91177308-0d34-0410-b5e6-96231b3b80d8

Use pseudo instructions for 2-register Neon instructions for scalar FP.
Partial fix for Radar 8711675.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121716 91177308-0d34-0410-b5e6-96231b3b80d8

Remove unused instruction class arguments.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121715 91177308-0d34-0410-b5e6-96231b3b80d8

Generalize BFI isel lowering a bit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121714 91177308-0d34-0410-b5e6-96231b3b80d8

add some DEBUG's.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121711 91177308-0d34-0410-b5e6-96231b3b80d8

In Thumb2, direct branches can be encoded as either a "short" conditional branch with a null predicate, or
as a "long" direct branch.  While the mnemonics are the same, they encode the branch offset differently, and
the Darwin assembler appears to prefer the "long" form for direct branches.  Thus, in the name of bitwise
equivalence, provide encoding and fixup support for it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121710 91177308-0d34-0410-b5e6-96231b3b80d8

Use 32-bit types for 32-bit values.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121709 91177308-0d34-0410-b5e6-96231b3b80d8

Trailing whitespace.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121708 91177308-0d34-0410-b5e6-96231b3b80d8

Fix sort predicate. qsort(3)'s predicate semantics differ from std::sort's. Fixes PR 8780.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121705 91177308-0d34-0410-b5e6-96231b3b80d8