Unused function - easier to throw away than fix.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27123 91177308-0d34-0410-b5e6-96231b3b80d8

Cast instruction not inserted into basic block.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27122 91177308-0d34-0410-b5e6-96231b3b80d8

Add a BUILD_VECTOR with unpack and interleave testcase.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27121 91177308-0d34-0410-b5e6-96231b3b80d8

Added missing (any_extend (load ...)) patterns.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27120 91177308-0d34-0410-b5e6-96231b3b80d8

Build arbitrary vector with more than 2 distinct scalar elements with a
series of unpack and interleave ops.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27119 91177308-0d34-0410-b5e6-96231b3b80d8

implement a bunch of intrinsics

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27118 91177308-0d34-0410-b5e6-96231b3b80d8

Move all Altivec stuff out into a new PPCInstrAltivec.td file.

Add a bunch of patterns for different datatypes, e.g. bit_convert, undef and
zero vector support.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27117 91177308-0d34-0410-b5e6-96231b3b80d8

Add some basic patterns for other datatypes

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27116 91177308-0d34-0410-b5e6-96231b3b80d8

add all supported formats to the vector register file

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27115 91177308-0d34-0410-b5e6-96231b3b80d8

remove extraneous lets

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27114 91177308-0d34-0410-b5e6-96231b3b80d8

Add a bunch of simple altivec intrinsics

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27113 91177308-0d34-0410-b5e6-96231b3b80d8

Add support for __builtin_altivec_vnmsubfp /vmaddfp

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27112 91177308-0d34-0410-b5e6-96231b3b80d8

Add support for __builtin_altivec_vnmsubfp

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27111 91177308-0d34-0410-b5e6-96231b3b80d8

When failing selection for an intrinsic, print this:

Cannot yet select: intrinsic %llvm.ppc.altivec.lvx

instead of this:

Cannot yet select: 0x9b047e0: v4i32,ch = INTRINSIC 0x9b04540:1, 0x9b04710, 0x9b04790, 0x9b04540

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27110 91177308-0d34-0410-b5e6-96231b3b80d8

#include Intrinsics.h into all dag isels

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27109 91177308-0d34-0410-b5e6-96231b3b80d8

Implement Intrinsic::getName

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27108 91177308-0d34-0410-b5e6-96231b3b80d8

Add a programatic interface to intrinsic names.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27107 91177308-0d34-0410-b5e6-96231b3b80d8

Codegen things like:
 <int -1, int -1, int -1, int -1>
and
 <int 65537, int 65537, int 65537, int 65537>

Using things like:
  vspltisb v0, -1
and:
  vspltish v0, 1

instead of using constant pool loads.

This implements CodeGen/PowerPC/vec_splat.ll:splat_imm_i{32|16}.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27106 91177308-0d34-0410-b5e6-96231b3b80d8

New tests for vsplti*

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27105 91177308-0d34-0410-b5e6-96231b3b80d8

X86 SSE1 cacheability support ops intrinsics

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27104 91177308-0d34-0410-b5e6-96231b3b80d8

Added SSE cachebility ops

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27103 91177308-0d34-0410-b5e6-96231b3b80d8

Instruction encoding bug

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27102 91177308-0d34-0410-b5e6-96231b3b80d8

Added a scalar to vector with zero extension testcase

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27101 91177308-0d34-0410-b5e6-96231b3b80d8

Add new intrinsic node definitions for tblgen use

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27100 91177308-0d34-0410-b5e6-96231b3b80d8

X86 SSE1 SIMD store intrinsics.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27099 91177308-0d34-0410-b5e6-96231b3b80d8

X86 SSE1 SIMD load intrinsics (movhps, movlps, and movups).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27098 91177308-0d34-0410-b5e6-96231b3b80d8

X86 SSE1 conversion operations intrinsics.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27097 91177308-0d34-0410-b5e6-96231b3b80d8

Added 128-bit packed integer subtraction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27096 91177308-0d34-0410-b5e6-96231b3b80d8

Added CVTTPS2PI.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27095 91177308-0d34-0410-b5e6-96231b3b80d8

Added CVTSS2SI.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27094 91177308-0d34-0410-b5e6-96231b3b80d8

X86 SSE1 comparison intrinsics.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27093 91177308-0d34-0410-b5e6-96231b3b80d8

X86 SSE1 arithmetic and logical operation intrinsics.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27092 91177308-0d34-0410-b5e6-96231b3b80d8

Support for scalar to vector with zero extension.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27091 91177308-0d34-0410-b5e6-96231b3b80d8

Change approach so that we get codegen for free for intrinsics.  With this,
intrinsics that don't take pointer arguments now work.  For example, we can
compile this:

int test3( __m128d *A) {
  return _mm_movemask_pd(*A);
}
int test4( __m128 *A) {
  return _mm_movemask_ps(*A);
}

to this:

_test3:
        movl 4(%esp), %eax
        movapd (%eax), %xmm0
        movmskpd %xmm0, %eax
        ret
_test4:
        movl 4(%esp), %eax
        movaps (%eax), %xmm0
        movmskps %xmm0, %eax
        ret

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27090 91177308-0d34-0410-b5e6-96231b3b80d8

fix inverted conditional

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27089 91177308-0d34-0410-b5e6-96231b3b80d8

D'oh - should be even numbered.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27088 91177308-0d34-0410-b5e6-96231b3b80d8

Added LDMXCSR

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27087 91177308-0d34-0410-b5e6-96231b3b80d8

ldmxcsr is a SSE instruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27086 91177308-0d34-0410-b5e6-96231b3b80d8

Added ldmxcsr intrinsic.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27085 91177308-0d34-0410-b5e6-96231b3b80d8

fix 80 column violations

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27084 91177308-0d34-0410-b5e6-96231b3b80d8

plug the intrinsics into the patterns for movmsk*

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27083 91177308-0d34-0410-b5e6-96231b3b80d8

Parse intrinsics correctly and perform type propagation.  This doesn't currently
emit the code to select intrinsics, but that is next :)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27082 91177308-0d34-0410-b5e6-96231b3b80d8

Add dwarf register numbering to register data.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27081 91177308-0d34-0410-b5e6-96231b3b80d8

Add support for dwarf register numbering.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27080 91177308-0d34-0410-b5e6-96231b3b80d8

Hack no more.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27079 91177308-0d34-0410-b5e6-96231b3b80d8

Make sure to initialize the TheDef field!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27078 91177308-0d34-0410-b5e6-96231b3b80d8

add another note

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27077 91177308-0d34-0410-b5e6-96231b3b80d8

add a note

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27076 91177308-0d34-0410-b5e6-96231b3b80d8

Move CodeGenIntrinsic implementation to CodeGenTarget.cpp with the rest of
the CodeGen* implementations.

Parse the MVT::ValueType for each operand of the intrinsics.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27075 91177308-0d34-0410-b5e6-96231b3b80d8

Specify the value type for each llvm type.  This needs work for pointers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27074 91177308-0d34-0410-b5e6-96231b3b80d8

Shuffle some includes around

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27073 91177308-0d34-0410-b5e6-96231b3b80d8

Pull in valuetypes.td here, we will use it shortly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27072 91177308-0d34-0410-b5e6-96231b3b80d8

Only to vector shuffle for {x,x,y,y} cases when SCALAR_TO_VECTOR is free.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27071 91177308-0d34-0410-b5e6-96231b3b80d8

expose intrinsic info to the targets.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27070 91177308-0d34-0410-b5e6-96231b3b80d8

Fix a bad JIT encoding of VPERM.  Why is VPERM D,A,B,C but vfmadd is D,A,C,B ??

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27069 91177308-0d34-0410-b5e6-96231b3b80d8

Like the comment says, prefer to use the implicit add done by [r+r] addressing
modes than emitting an explicit add and using a base of r0.  This implements
Regression/CodeGen/PowerPC/mem-rr-addr-mode.ll

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27068 91177308-0d34-0410-b5e6-96231b3b80d8

New testcase

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27067 91177308-0d34-0410-b5e6-96231b3b80d8

Tweak a comment.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27066 91177308-0d34-0410-b5e6-96231b3b80d8

Fix indent.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27065 91177308-0d34-0410-b5e6-96231b3b80d8

Clean up some commentary.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27064 91177308-0d34-0410-b5e6-96231b3b80d8

Rename for truth in advertising.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27063 91177308-0d34-0410-b5e6-96231b3b80d8

Fixed some grammer and spelling.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27062 91177308-0d34-0410-b5e6-96231b3b80d8

Zero vector testcase

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27061 91177308-0d34-0410-b5e6-96231b3b80d8

Disable the i32->float G5 optimization.  It is unsafe, as documented in the
comment.

This fixes 177.mesa, and McCat/09-vor with the td scheduler.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27060 91177308-0d34-0410-b5e6-96231b3b80d8

add support for using vxor to build zero vectors.  This implements
Regression/CodeGen/PowerPC/vec_zero.ll

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27059 91177308-0d34-0410-b5e6-96231b3b80d8

new testcase

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27058 91177308-0d34-0410-b5e6-96231b3b80d8

Add a facility for invoking the llvm-config tool when linking a program.
This facility allows LLVMLIBS to be specified with something like:
LLVMLIBS = config --libs jit
instead of:
LLVMLIBS = JIT
with the same effect. However, the llvm-config utility is much more versatile
than the single keyword approach. Note that "config" is the keyword after
which any arguments to llvm-config are allowed. When llvm-config is tested
and working well, we'll start using this and drop support for the JIT
keyword.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27057 91177308-0d34-0410-b5e6-96231b3b80d8

Handle BUILD_VECTOR with all zero elements.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27056 91177308-0d34-0410-b5e6-96231b3b80d8

prefer to generate constant pool loads over splats.  This prevents us from
using a splat for {1.0,1.0,1.0,1.0}

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27055 91177308-0d34-0410-b5e6-96231b3b80d8

Fix a typo, thanks to Gabor Greif

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27054 91177308-0d34-0410-b5e6-96231b3b80d8

fix spello

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27053 91177308-0d34-0410-b5e6-96231b3b80d8

Fix spello

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27052 91177308-0d34-0410-b5e6-96231b3b80d8

add the actual cost to the debug info

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27051 91177308-0d34-0410-b5e6-96231b3b80d8

fix two spellos

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27050 91177308-0d34-0410-b5e6-96231b3b80d8

Gabor points out that we can't spell. :)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27049 91177308-0d34-0410-b5e6-96231b3b80d8

Remove a spurious <table> tag.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27045 91177308-0d34-0410-b5e6-96231b3b80d8

All v2f64 shuffle cases can be handled.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27044 91177308-0d34-0410-b5e6-96231b3b80d8

Fix headers

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27043 91177308-0d34-0410-b5e6-96231b3b80d8

Minor corrections.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27042 91177308-0d34-0410-b5e6-96231b3b80d8

Minor corrections.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27041 91177308-0d34-0410-b5e6-96231b3b80d8

More efficient v2f64 shuffle using movlhps, movhlps, unpckhpd, and unpcklpd.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27040 91177308-0d34-0410-b5e6-96231b3b80d8

A new entry

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27039 91177308-0d34-0410-b5e6-96231b3b80d8

Add a v2f64 shuffle case.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27038 91177308-0d34-0410-b5e6-96231b3b80d8

Get JIT/Interpreter working on Windows again.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27037 91177308-0d34-0410-b5e6-96231b3b80d8

legalize vbit_convert nodes whose result is a legal type.
Legalize intrinsic nodes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27036 91177308-0d34-0410-b5e6-96231b3b80d8

Lower target intrinsics into an INTRINSIC node

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27035 91177308-0d34-0410-b5e6-96231b3b80d8

Ignore the lexer output.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27034 91177308-0d34-0410-b5e6-96231b3b80d8

Ignore the burg output files.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27033 91177308-0d34-0410-b5e6-96231b3b80d8

fix some bogus assertions: noop bitconverts are legal

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27032 91177308-0d34-0410-b5e6-96231b3b80d8

Get Visual Studio happy again.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27031 91177308-0d34-0410-b5e6-96231b3b80d8

Add a vector shuffle test case

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27027 91177308-0d34-0410-b5e6-96231b3b80d8

Handle more shuffle cases with SHUFP* instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27024 91177308-0d34-0410-b5e6-96231b3b80d8

Lower BUILD_VECTOR to VECTOR_SHUFFLE if there are two distinct nodes (and if
the target can handle it). Issue two SCALAR_TO_VECTOR ops followed by a
VECTOR_SHUFFLE to select from the two vectors.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27023 91177308-0d34-0410-b5e6-96231b3b80d8

extract some more information from the intrinsic table

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27022 91177308-0d34-0410-b5e6-96231b3b80d8

Remove the interpreter component as its not working at the moment.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27021 91177308-0d34-0410-b5e6-96231b3b80d8

Identify the INTRINSIC node

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27020 91177308-0d34-0410-b5e6-96231b3b80d8

add a new intrinsic node

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27019 91177308-0d34-0410-b5e6-96231b3b80d8

Add a couple simple intrinsics for intel.  Fix the v2f64 definition.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27018 91177308-0d34-0410-b5e6-96231b3b80d8

Add llvm-config to the index.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27017 91177308-0d34-0410-b5e6-96231b3b80d8

Ignored generated files.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27016 91177308-0d34-0410-b5e6-96231b3b80d8