arm: dts: rk322x-android: enable u2phy1 otg-port

Change-Id: Ib6caa6366704509ca5c708a6bfee0e9fc6d26abe
Signed-off-by: William Wu <william.wu@rock-chips.com>

arm: dts: rockchip: add u2phy1 otg-port node for rk322x SoC

Change-Id: I42efd4227428df38c643c174fb2babcd61064a72
Signed-off-by: William Wu <william.wu@rock-chips.com>

phy: rockchip-inno-usb2: add cfgs for phy1 port1 of rk322x SoC

This patch adds port configuration for usb2 phy1 port1 of rk322x
SoC. For the current rockchip inno usb2 phy driver framework, it
can only support usb2 phy which comprises with one otg-port and
one host-port.

However, rk322x SoC usb2 phy1 comprises with two host-ports, so
we use otg id index for phy1 port1 configuration, and make phy1
port1 work the same as otg-port host mode.

Change-Id: Iaa10c2438c6b7b052c7f3830252ba4ebd91ff23f
Signed-off-by: William Wu <william.wu@rock-chips.com>

ARM: rockchip: Add workaround for unknown write of thread_info

We see the cpu of thread_info was changed by unknown reason sometimes,
which cause rq spinlock deadlock while schedule. Until we found the
root cause, we have to add this workaround.

Change-Id: Ib943ccb47a57fe4b267a1da853366363cd7f1f52
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>

PM / devfreq: rockchip_dmc: add unify params for ddr frequency scanning.

1. add unify params for ddr frequency scanning.
2. add dram side and phy side odt disable frequency configurate
independent.

Change-Id: Ied97dbee8d30a1a6e95d4c252986121092c484d8
Signed-off-by: Tang Yun ping <typ@rock-chips.com>

clk: rockchip: using unify parameters for ddr frequency scanning.

Change-Id: Ibd3befd3cd674af263402f6984ee6d605eb087c8
Signed-off-by: Tang Yun ping <typ@rock-chips.com>

cpufreq: rockchip: limit frequency when reboot

If i2c driver adds a shutdown callback function, the callback will be
executed before cpu's shutdown callback when reboot system, it will
fail to scale voltage like the following.
rk3x-i2c ff650000.i2c: Access denied - device already shutdown
rk3x-i2c ff650000.i2c: Access denied - device already shutdown
rk3x-i2c ff650000.i2c: Access denied - device already shutdown
rk3x-i2c ff650000.i2c: Access denied - device already shutdown
cpu cpu4: _set_opp_voltage: failed to set voltage
(950000 950000 1350000 mV):-5

So add a reboot notifier to limit frequency before i2c's shutdown callback,
and the cpu's shutdown callback will do nothing.

Change-Id: Ic5bb21b511c6f799dc62fd9db237d90522b7d4ee
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>

net: stmmac: dwmac-rk: read mac address from devinfo first

Change-Id: I2888dcfc57c2e5a266fdf1058f9ab70e04034f22
Signed-off-by: Zhangbin Tong <zebulun.tong@rock-chips.com>

cpufreq: rockchip: optimize rockchip_cpufreq_driver_init()

Actually there is no need to use two loops.

Change-Id: Ieafdc265307e21fc7195f3d80b42483a2d53d413
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>

ARM64: dts: rockchip: modify battery sample register value of rk3368-p9 according to hardware board

Change-Id: I50fc124f06b8c2b5af20d5e44a93f68d28d748a0
Signed-off-by: Zorro Liu <lyx@rock-chips.com>

ARM64: dts: rk3399: android: add compatible for stb_devinfo node

Change-Id: Ib45c5ff21f884fba12e39be63740f90bfc4bbc27
Signed-off-by: Zhangbin Tong <zebulun.tong@rock-chips.com>

PM / devfreq: rockchip_dmc: Avoid glitches due to slow CPU

We weren't giving enough time for DMC to change frequencies
when the CPU was running slow.

Change-Id: I84e1a4ad7b5ccddafb0016f3d5d6eef147a58591
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>

PM / devfreq: Lock CPU online/offline in rockchip_dmcfreq_target()

To protect against races with concurrent CPU online/offline, call
get_online_cpus() before change frequency.

Change-Id: I5b97cd7eff6a1c4828ab30bc165fb2aa8b460bb3
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>

arm64: dts: rk3368: p9: set mipi_dsi_host delay 200ms

Change-Id: Ibed9c624072f590ed2aeee8529e133a505624e8d
Signed-off-by: Wu Liangqing <wlq@rock-chips.com>

arm64: dts: rk3368-sheep: add rk818 battery node

Change-Id: I7e0f0ea93a2019ea022c9fe8e72f412af0ec6be9
Signed-off-by: Xu Jianqun <jay.xu@rock-chips.com>

arm: dts: rk322x-android: update shut mode and enable this module

gpio is not connected by default and we suggest cru mode as the default
shut mode.

Change-Id: I74593092b145e51e5f5b52ab028e650b7fe67f5e
Signed-off-by: Rocky Hao <rocky.hao@rock-chips.com>

arm: dts: rockchip: rk322x: update tsadc's frequence setting

update freq of tsadc's working clock as 32768 hz, if not set, tsadc
will work at a default frequence.

Change-Id: I04f3ee230819af1fce44518b5cbee7700c4d67fd
Signed-off-by: Rocky Hao <rocky.hao@rock-chips.com>

drivers: inv_mpu: remove no use debug

Change-Id: Ife1fae1323e2ed262a2f7063e5bb313cb304033f
Signed-off-by: Zorro Liu <lyx@rock-chips.com>

UPSTREAM: dma-buf: Add ioctls to allow userspace to flush

The userspace might need some sort of cache coherency management e.g. when CPU
and GPU domains are being accessed through dma-buf at the same time. To
circumvent this problem there are begin/end coherency markers, that forward
directly to existing dma-buf device drivers vfunc hooks. Userspace can make use
of those markers through the DMA_BUF_IOCTL_SYNC ioctl. The sequence would be
used like following:
     - mmap dma-buf fd
     - for each drawing/upload cycle in CPU 1. SYNC_START ioctl, 2. read/write
       to mmap area 3. SYNC_END ioctl. This can be repeated as often as you
       want (with the new data being consumed by the GPU or say scanout device)
     - munmap once you don't need the buffer any more

BackPort:
  upstream kernel change dma-buf api with the commit(831e9da
  dma-buf: Remove range-based flush), avoid effect too much to
  current kernel, Just compatible dma-buf api to current version.

v2 (Tiago): Fix header file type names (u64 -> __u64)
v3 (Tiago): Add documentation. Use enum dma_buf_sync_flags to the begin/end
dma-buf functions. Check for overflows in start/length.
v4 (Tiago): use 2d regions for sync.
v5 (Tiago): forget about 2d regions (v4); use _IOW in DMA_BUF_IOCTL_SYNC and
remove range information from struct dma_buf_sync.
v6 (Tiago): use __u64 structured padded flags instead enum. Adjust
documentation about the recommendation on using sync ioctls.
v7 (Tiago): Alex' nit on flags definition and being even more wording in the
doc about sync usage.
v9 (Tiago): remove useless is_dma_buf_file check. Fix sync.flags conditionals
and its mask order check. Add <linux/types.h> include in dma-buf.h.

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: David Herrmann <dh.herrmann@gmail.com>
Cc: Sumit Semwal <sumit.semwal@linaro.org>
Reviewed-by: Stéphane Marchesin <marcheu@chromium.org>
Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
Signed-off-by: Tiago Vignatti <tiago.vignatti@intel.com>
Reviewed-by: David Herrmann <dh.herrmann@gmail.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1455228291-29640-1-git-send-email-tiago.vignatti@intel.com
(cherry picked from commit c11e391da2a8fe973c3c2398452000bed505851e)

Change-Id: I92916babe7fb0ab3bf3ce9dc966408f2e05fe83d
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>

rockchip: clk: rk3368: remove the flag ROCKCHIP_PLL_SYNC_RATE for CPLL

to slove the display shaking, when uboot logo display to kernel show.

Change-Id: I5856581fabd0171be09993878ffb4ef1af0fb204
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

firmware: rockchip: use 'nsec_ctx->und_lr' to deliver fiq break point's PC

'nsec_ctx->mon_lr' is not the fiq break point's PC, because it will
be override as 'sip_fiq_debugger_uart_irq_tf_cb' for optee-os to
jump to fiq_debugger handler. As 'nsec_ctx->und_lr' is not used for
kernel, optee-os uses it to deliver fiq break point's PC.

Change-Id: I5a831638e8228766d03d92674e3e29facdd116f8
Signed-off-by: chenjh <chenjh@rock-chips.com>

arm64: dts: rockchip: rk3328-evb: add clk dts node for rk805

Change-Id: I30f061a8325d7207133bfd0ab7d82b79664262cf
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

arm: dts: rk3229-echo-v10: add clk dts node for rk805

Change-Id: Idff25c5e311f282c67f8dbabbd104019f19bbb6a
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

mfd: rk808: add rk808-clkout mfd cell for rk805

support rk805 two clk output,xin32k and rk805-clkout2.

Change-Id: If4f820f53feaf6ab2804f4acd0cce925667b7bc0
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

Revert "arm64: rockchip_defconfig: enable CONFIG_IKCONFIG"

This reverts commit 28f4152aad7fc402f6f545f07f4193aac7a05087.

For pass Android 7.1 CTS:
android.security.cts.KernelSettingsTest#testNoConfigGz

Change-Id: I9bd7d4c6c06b7d43fa51a7f02eecca8cedc61c1d
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>

Revert "ARM: rockchip_defconfig: enable CONFIG_IKCONFIG"

This reverts commit b90c069d1edf02a11533cf6ba401316e36b6702b.

For pass Android 7.1 CTS:
android.security.cts.KernelSettingsTest#testNoConfigGz

Change-Id: Ia45a95bbb9aafaf0b38b7bd4647f20878403eaae
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>

arm: dts: rk3288: add dts for rk3288 evb with act8846 and edp

Change-Id: I861ebd4f6fbe04809f1d450d1a6fd139125c9f67
Signed-off-by: Xu Jianqun <jay.xu@rock-chips.com>

arm64: dts: rk3399-android-6.0: use ion for iep

Change-Id: If3dd5da95abb462ac15d56de26aaeff1b95f5a65
Signed-off-by: buluess.li <buluess.li@rock-chips.com>

arm: dts: add gpio power-key support for rk322x SoC

Change-Id: I45d6e0ffe5444b26165324048c0e88d6fca19bab
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>

ARM64: dts: rockchip: reduce cma size of rk3368-android

Change-Id: I33407879b63acfaf6da994a5c99633b3e2ad388b
Signed-off-by: Zorro Liu <lyx@rock-chips.com>

soc: rockchip: add devinfo parser driver

Change-Id: I8e16d5ee8a1456de43e46e68bee60e7fb2a7b266
Signed-off-by: Zhangbin Tong <zebulun.tong@rock-chips.com>

ARM64: dts: rk3399: android: add memory reserved for deviceinfo

Change-Id: Iff4cdc07f1a79d832af85dc23ed1001002fe2e6a
Signed-off-by: Zhangbin Tong <zebulun.tong@rock-chips.com>

ARM: dts: rk322x: fix i2s1 pinctrl error

Change-Id: I29fa27ea159b86d3cdfbaf6d9c620e53bc52afd9
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>

ARM: dts: rk322x: add spdif node

Change-Id: Id8ccff720d3e42e0df8fa8fd5007127fa9af2147
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>

ASoC: rockchip: add support for rk3228 spdif

Change-Id: I3f0ae976ef055086f48c2b95b5e45a9eac7487ad
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>

drm/rockchip: vop: add line_flag 0/1 for ddr freq change

Change-Id: Icae9fe3d3600a478f68220545c17b393b4aff1ec
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>

mfd: fusb302: Don't mistake meaningful packets for Good_CRC

If a partner port sends a packet at approximately the same time as we
send a packet, we may end up with the initial packet followed by the
GOOD_CRC reply in our HW FIFO. Don't automatically discard the first
packet in the FIFO. Instead, discard the packet only if it's a GOOD_CRC
packet. And, modify our get_message function to automatically discard
GOOD_CRC in search of a meaningful packet.

In addition, due to interrupt latency, we can't rely on receiving one
interrupt per incoming packet. If our Rx FIFO is non-empty, assume that
it contains at least one packet.

Change-Id: Iaad80a4c55eea3e9e2791d81d7c5d28ce97bd2f5
Signed-off-by: zain wang <wzz@rock-chips.com>

ARM64: dts: rk3368: add rk3368-sheep-lvds.dts for sheep board

Change-Id: Iaf65b8c8f928397e1a3641a7521ee2efed230d31
Signed-off-by: Huang Jiachai <hjc@rock-chips.com>

arm: rockchip_defconfig: enable CONFIG_KEYBOARD_GPIO

This adds enable CONFIG_KEYBOARD_GPIO to support gpio-keys driver.

Change-Id: Ib2e127a3d017ad69b1bf6c0b0a795d0bce44af0e
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>

drm/rockchip: vop: correct rk322x vop define

Change-Id: If4c3b2e54f3621f7b1120401d9a049d780aa9b4f
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>

arm: dts: rk322x: Add io-domain support for rk3229-evb and rk3229-echo-v10

The power domain of VCCIO3 is selected from maskrom,
so we don't need to configure it.

Change-Id: I11f87fe6f178943daa5ec9dcc22f4f505fe58163
Signed-off-by: David Wu <david.wu@rock-chips.com>

arm: dts: rk322x: Add io-domain node

Change-Id: I1707bc7e4ed166b1aee14d69c7e25a57ab535d83
Signed-off-by: David Wu <david.wu@rock-chips.com>

PM / AVS: rockchip-io: Add rk322x io-domains support

Change-Id: Iaa91c932fdd9a9589945b0c6e19bc73517f7b322
Signed-off-by: David Wu <david.wu@rock-chips.com>

ARM: dts: rk3229-evb: enable GPU device

Change-Id: Ifab6284e56d1e833990b53d1aa555f55b520c955
Signed-off-by: chenzhen <chenzhen@rock-chips.com>

arm: dts: rk3229-echo-v10: enable GPU device

Change-Id: I4336bd134afea2b8ad55ebb104c877548c16b582
Signed-off-by: chenzhen <chenzhen@rock-chips.com>

arm: dts: rk322x: add mali-400 GPU device

Change-Id: I4fb5d27a34e57bb17db2c79ffdc655223ce8c338
Signed-off-by: chenzhen <chenzhen@rock-chips.com>

ARM: rockchip_defconfig: enable driver for Mali400 GPU

Change-Id: Idcccf39fc0a5d2d340325e1b3445c8c0d3dcbcc3
Signed-off-by: chenzhen <chenzhen@rock-chips.com>

ARM: dts: rk322x: add 'nvmem-cells' property for opp_table0

This patch adds nvmem-cells property to opp_table0 node so that
cpufreq driver can get cpu leakage value.

Change-Id: Ic39525de46762dfe867ecb86123be6fa7ccad95c
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>

ARM: dts: rockchip: add efuse device node for rk322x

Add a efuse node in the device tree for the rk322x SoC.

Change-Id: I9a771c2065bb222b754f5a37b193edd4abb3f3a7
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>

arm64: rockchip_defconfig: enable HDMI_ANALOG

Change-Id: Icae9ce3e01f063c8b6e169b9d386b6eeeed54961
Signed-off-by: zhangjun <zhangjun@rock-chips.com>

ASoC: rockchip: add machine driver for built-in hdmi and codec IC

this patch is used for rockchip built-in HDMI and audio codec
IC which are wired to the same i2s line(such as rk3368).
so we use a DAI link CPU to multicodecs.

Change-Id: Ibc5fdeb2091836dc28675aacdc099d76e0b7d752
Signed-off-by: zhangjun <zhangjun@rock-chips.com>

dt-bindings: suspend: rockchip: add PMU_USB_LINESTAE_WAKEUP_EN config for wakeup

Change-Id: I73b992b57344f24eb37b360bc479264996ff72d1
Signed-off-by: shengfei Xu <xsf@rock-chips.com>

PM / devfreq: rockchip_dmc: Fix error handling

It never has the mutex_lock counterpart before goto.

Change-Id: I937e79bc65433cb1c173fe0cb221e7d69586046c
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>

arm: dts: rk3288-evb: enable rockchip-suspend node

Change-Id: I1bc5f75d3bf49b7f5a532d7dbe7206edc6932c36
Signed-off-by: shengfei Xu <xsf@rock-chips.com>

arm: dts: rk3288: add rockchip-suspend node

Change-Id: Id5700548a6034248ed5ad3226dd652d0833eec13
Signed-off-by: shengfei Xu <xsf@rock-chips.com>

soc: rockchip: support rk3288 pm config

Change-Id: Icbd23af68bdf7a4fcad59a5d227988a13b2873af
Signed-off-by: shengfei Xu <xsf@rock-chips.com>

nvmem: rockchip-efuse: add support for rk322x-efuse

This adds the necessary data for handling efuse on the rk322x.

Change-Id: Iadd37923f5949a03630a936d5a41b955d443b2d8
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>

ARM: dts: rk3229: add cpu-supply property for cpu node in evb board

This patch adds the cpu-supply property so that cpu can do dvfs

Change-Id: I6cfc1c8e467652ad9b748c6a9980b00006181910
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>

ARM: dts: rk3229: add cpu-supply property for cpu node in echo-v1 board

This patch adds the cpu-supply property so that cpu can do dvfs

Change-Id: I5edff7fabd1de23407e8fcb7d70e3b0eeee2ee0e
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>

ARM: dts: rk3229: add a new cpu opp table

This patch adds some new frequencies for rk3229 boards

Change-Id: Ie35efc3f04350bcfd1eae31a72adfc9166bef781
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>

ARM: dts: rk322x: add operating-points-v2 property for cpu

This patch adds a new opp table for cpu

Change-Id: I59384ab8ab649ca4672adf64c52f16da76777ce4
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>

clk: rockchip: rk3228: add 1464000000 into cpuclk rate table

This patch adds 1464000000Hz for armclk

Change-Id: I3e4c18acf13036b778f18fe166ae47682a97feeb
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>

dt-bindings: rockchip: vop: add gamma_table range

Change-Id: Iafbff319d33c9436963572e05911ccfe676a4852
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>

FROMLIST: drm: Pass CRTC ID in userspace vblank events

With the atomic API, it is possible that a single commit affects
multiple crtcs. If the user requests an event with that commit, one
event will be sent for each CRTC, but it is not possible to distinguish
which crtc an event is for in user space. To solve this, the reserved
field in struct drm_vblank_event is repurposed to include the crtc_id
which the event is for.

The DRM_CAP_CRTC_IN_VBLANK_EVENT is added to allow userspace to query if
the crtc field will be set properly.

[daniels: Rebased, using Maarten's forward-port.]

Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
Signed-off-by: Daniel Stone <daniels@collabora.com>
Cc: Maarten Lankhorst <maarten.lankhorst@intel.com>
Reviewed-by: Sean Paul <seanpaul@chromium.org>
(am from https://patchwork.kernel.org/patch/9662099/)

Change-Id: Ibe6949782e5df5363d4eaa3e98b3ff413239cf26
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>

mfd: fusb302: ignored the timeout if vdm got the message.

The PD spec define the source should ensure that a message requesting
a response is responded within 30ms(tSenderResponse). But if the
message responded is received close to 30ms, we may hit the case:

tcpm_get_message(); //get the data and close to 30ms
... takes about 600us, meanwhile the 30ms timer came.
auto_vdm_machine
vdm_send... //we get the message, but timeout.

So, let's ignored the timeout if we get the message.

Change-Id: I64ced1bd2d32d8ef996dcec27cf35c3e333386f8
Signed-off-by: zain wang <wzz@rock-chips.com>

arm: dts: rockchip: add gamma table support for rk322x

Change-Id: I9aa8af01bd989ff244153d53c8b9b8ca06d3f834
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>

arm: dts: rockchip: add gamma table support for rk3288

Change-Id: Idb4cd93b8a696925ac56b98c1619999949e6fd84
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>

arm64: dts: rockchip: add gamma table support for rk3368

Change-Id: Ia0390aa0ffe99a2c2b6ba82ecd83610683d49eac
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>

arm64: dts: rockchip: add gamma table support for rk3399

Rk3399 vopb's gamma table size is 1024, vopl's gamma
table size is 256

Change-Id: Iea9cd70f82dfa9c9c8ae53a24c8153eebb981e7a
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>

drm/rockchip: add support for gamma table

Introduce support for rockchip gamma table,

Rockchip have two version gamma table design:
The old version design was introduced by Dominik Behr's gamma patch
(https://chromium-review.googlesource.com/272209):
 Gamma table has to be uploaded when the LUT is disabled which only takes
 effect at the end of a frame, therefore actual hardware updates is done
 from a worker and can take more than one frame.

In order to solve gamma table switch issues, after rk3399,
H/W add a gamma table update mechanism, can update without lut disable.

And gamma table's size also has two version:
  one is 10 bit per component, 1024 entries,
  the other one is 8 bit per component, 256 entries

Change-Id: I8145d1c42a28d57f11e95d24be2341011360334d
Signed-off-by: Dominik Behr <dbehr@chromium.org>
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>

PM / devfreq: rockchip_dmc: avoid waiting for vop line flag indefinitely

It may disable vop_crtc when scaling frequency, in this case,
devfreq thread will wait for vop line flag indefinitely, the
system will crash.

Change-Id: I7043b285c329ff23e2fc9c5b5f3a165c37ef6378
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>

drm/rockchip: vop: export rockchip_drm_register_notifier_to_dmc

This function registers a notifier to dmc devfreq, devfreq thread will
lock the mutex of vop when scaling frequency, so vop_crtc will not be
disabled when it is waiting for line flag.

Change-Id: I886e5dc5d36a0f14f35662cec3423a2c5550a7a6
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>

drm/rockchip: vop: add vop enable/disable mutex lock

It may disable vop_crtc when waiting for line flag, in this case,
we would not get line flag any more. So the lock should be added
to prevent rockchip_wait_line_flag() from vop_crtc_disable();

Change-Id: I312fd46e64006bf69e3c57f54513230b90866e21
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>

camera: rockchip: camsys driver v0.0x21.0xf

add reference count for marvin

Change-Id: Ic410da2524a8972d782ccfdcb121e1727b02e9d8
Signed-off-by: zhangyunlong <dalon.zhang@rock-chips.com>

camera: rockchip: fix some compiled errors and warn

fix spin_unlock error use and some potential problems.

Change-Id: I860c225f2acb5e28827ad3f6b702b0dc7828bb0f
Signed-off-by: xcq <shawn.xu@rock-chips.com>

ARM: rockchip_defconfig: default to enable rockchip dmc

Change-Id: Ia52708079d41379d0c530b08d6a3a6bf109ee98c
Signed-off-by: Tang Yun ping <typ@rock-chips.com>

PM / devfreq: rockchip_dmc: add support for rk3288

This adds the necessary data for handling dmcfreq on the rk3288.

Change-Id: I042222f899d03ec1832ac47b48db8c6c46c3b0d3
Signed-off-by: Tang Yun ping <typ@rock-chips.com>

PM / devfreq: event: add support for rk3288 dfi

This adds the necessary data for handling dfi on the rk3288.
Access the dfi via registers provided by GRF (general register
files) module.

Change-Id: Ic7241af3c20a269ab362055dea04d260e01c50de
Signed-off-by: Tang Yun ping <typ@rock-chips.com>

clk: rockchip: support setting ddr clock via SIP Version 2 APIs

1. Add support setting ddr clock via SIP Version 2 APIs
2. RK3288 using SIP Vision 2.

Change-Id: I935e43b1885a96650dc86e3eb6d79de6795062a9
Signed-off-by: Tang Yun ping <typ@rock-chips.com>

sip: rockchip: fix bus about make kernel failure

When undefine "CONFIG_ROCKCHIP_SIP", define an empty sip function
to avoid make kernel failure.

Change-Id: Id6bcf1cec1c11f09511852e015631d14279ca8bc
Signed-off-by: Tang Yun ping <typ@rock-chips.com>

drm: add drm_device_get_by_name support

Change-Id: Ifbd0f403ca2302e9329a16d7b69db5ee056cadf7
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>

Revert "fiq debugger: add resume for debug uart"

This reverts commit 0e7d751d6c004970348bdacb6961e06e7775cb92.

If enable no console suspend, it will do resume when printing log,
which causes problem. Remove resume of kernel, and add resume of
trust firmware or other power management code.

Change-Id: I3e8e704140134a6aad5c0eb2f14fde36fb108ad3
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>

arm: dts: add vdd_arm and vdd_log regulator for rk3229-evb

Change-Id: I1a0bbee3e5b9a43f2a79285c04497ec598697404
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>

arm64: dts: rk3368-android: revert to use uart2 for debug

Change-Id: I5e6c88e185a2ad39b082ad4b989589cd46ecb874
Signed-off-by: Xu Jianqun <jay.xu@rock-chips.com>

net: stmmac: The netif_device_attach() should be called after napi_enable()

If the netif_device_attach() is called earlier, the state of dev_queue is
waked, txtimer might be modified, and the txtimer is added at same time.
It might make run_timer_softirq crashed, because the timer is be detached
twice together.

Change-Id: I31dde4e940bddcc36372ca1f4a8313c0389d4e6b
Signed-off-by: David Wu <david.wu@rock-chips.com>

arm: dts: simplified rk3229 board configs.

Move EMMC and UART configs from every board DTS to a DTSI file.

Change-Id: If2fd49b9243b879ae89e172f55903eedfd4f3981
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>

arm: dts: add watchdog and uart2 related for rk322x SoC

Add another GPIO sets for UART2 since the old ones are conflict
with SDMMC, also add watchdog support.

Change-Id: Ib0f1472b9a7760e15e1b83e103f65f43e3642643
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>

ARM: dts: rockchip: remove dev_mode from rk3288

Since there is no combo device at RK3288, no need to
use this property anymore.

Change-Id: I56434161c4167fc048e4956e97b29617367e28f6
Signed-off-by: Randy Li <randy.li@rock-chips.com>

clk: rockchip: rk3288: always enable gpll_ddr for ddrc.

When ddr frequency scanning, need to switch to gpll for saving
times.

Change-Id: Ibb7e4ed1fa4babaf65e1d98c8a0891766cea63de
Signed-off-by: Tang Yun ping <typ@rock-chips.com>

sip: rockchip: add SHARE_PAGE_TYPE_DDR for ddr frequency scanning.

Change-Id: I7b9c81912e15bf2cea6739a051e5f466ba759d77
Signed-off-by: Tang Yun ping <typ@rock-chips.com>

phy: rockchip-inno-usb2: increase otg sm work first schedule time

In rockchip inno usb2 phy driver, we use otg_sm_work to
dynamically manage power consumption for phy otg-port.
If the otg-port works as peripheral mode and doesn't
communicate with usb host, we will suspend phy.

But once suspend phy, the phy no longer has any internal
clock running, include the utmi_clk which supplied for
usb controller. So if we suspend phy before usb controller
init, it will cause usb controller fail to initialize.

Specifically, without this pathch, the observed order is:
 1. unplug usb cable
 2. start system, do dwc2 controller probe
 3. dwc2_lowlevel_hw_enable()
    - phy_init()
     - rockchip_usb2phy_init()
      - schedule otg_sm_work after 2s
        put phy in suspend, and close utmi_clk
 4. dwc2_hsotg_udc_start() - fail to initialize the usb core

Generally, dwc2_hsotg_udc_start() can be called within 5s
after start system on rockchip platform, so we increase the
the first schedule delay time to 6s for otg_sm_work afer usb
controller calls phy_init(), this can make sure that the usb
controller completes initialization before phy enter suspend.

Change-Id: I40a7f6b24620e49a1273cb9c5051d62efb62810d
Signed-off-by: William Wu <william.wu@rock-chips.com>

mailbox: rk3368: fix error setting if mbox_msg is null

Fix the error dump:

[19252.682822] Unable to handle kernel NULL pointer dereference at
virtual address 00000020
[19252.682834] pgd = ffffff800935d000
[19252.682844] [00000020] *pgd=0000000077ffe003, *pud=0000000077ffe003,
*pmd=0000000000000000
[19252.682852] Internal error: Oops: 96000005 [#1] PREEMPT SMP
[19252.682863] Modules linked in: pvrsrvkm(O)
[19252.682872] CPU: 1 PID: 59 Comm: irq/32-ff6b0000 Tainted: G        W
O    4.4.55 #34
[19252.682875] Hardware name: Rockchip rk3368 p9 board (DT)
[19252.682880] task: ffffffc074cf8c40 ti: ffffffc074d04000 task.ti:
ffffffc074d04000
[19252.682894] PC is at mbox_chan_received_data+0xc/0x20
[19252.682901] LR is at rk3368_mbox_isr+0xb0/0xd0

Change-Id: I1873d6a7e7d1390d2c2c44a77c120d1a02614fdc
Signed-off-by: Xu Jianqun <jay.xu@rock-chips.com>

phy: rockchip-inno-usb2: add a delay after phy resume

When resume phy, it need about 1.5 ~ 2ms to wait for
utmi_clk which used for USB controller to become stable.

Change-Id: I319a28069b4b3381f22cc34567226f341e948bd4
Signed-off-by: William Wu <william.wu@rock-chips.com>

ARM64: dts: rk3368-android: enable fiq mode

If this patch is used, dedicated trust firmwart is necessary.

Change-Id: I72ca3b1b722c4076f589341e40efcbeeb5a07a58
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>

rk_fiq_debugger: remove "read signal irq from dts directly"

Change-Id: I1f531ce2f58b33d5501f8446ad393e7ac4f27ef0
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>

arm: dts: rk322x-android: enable usb otg controller and its phy

Change-Id: Ie03c7fe388360b0285d2a6eb0a455f5ed28e74c4
Signed-off-by: William Wu <william.wu@rock-chips.com>

phy: rockchip-inno-usb2: add otg-port support for rk322x SoC

This patch adds USB 2.0 PHY otg-port configuration for rk322x
SoC, this otg-port can be used for USB 2.0 OTG interface.

Change-Id: I7f2e362292edb45078a16d1a9665e3bdccc54814
Signed-off-by: William Wu <william.wu@rock-chips.com>

arm: dts: rockchip: add u2phy otg-port and dwc2 ctrl nodes for rk322x SoC

This patch adds dwc2 controller and its phy nodes for rk322x SoC.

Change-Id: I29779baf92c28154ad342e234e8a5582984b8a12
Signed-off-by: William Wu <william.wu@rock-chips.com>

ARM: dts: rk322x: add vop display node

Change-Id: Ic26431540260c758b6872020c36a41efdb2d82f2
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>

OP-TEE: use sema_init instead of __SEMAPHORE_INITIALIZER

Fix lockdep warning:
the code is fine but needs lockdep annotation.
turning off the locking correctness validator.
CPU:rk3288:/ $  0 PID: 234 Comm: tee-supplicant Not tainted 4.4.64 #51
Hardware name: Rockchip (Device Tree)
[<c0110018>] (unwind_backtrace) from [<c010c048>] (show_stack+0x10/0x14)
[<c010c048>] (show_stack) from [<c04194a8>] (dump_stack+0x9c/0xd4)
[<c04194a8>] (dump_stack) from [<c018321c>] (__lock_acquire+0x638/0x1c10)
[<c018321c>] (__lock_acquire) from [<c01850ec>] (lock_acquire+0x1d0/0x29c)
[<c01850ec>] (lock_acquire) from [<c0bc0f3c>] (_raw_spin_lock_irqsave+0x50/0x64)
[<c0bc0f3c>] (_raw_spin_lock_irqsave) from [<c017e148>] (down_interruptible+0xc/0x48)
[<c017e148>] (down_interruptible) from [<c03cd72c>] (tee_supp_read+0x74/0x154)
[<c03cd72c>] (tee_supp_read) from [<c025d638>] (__vfs_read+0x2c/0xf0)
[<c025d638>] (__vfs_read) from [<c025de30>] (vfs_read+0x84/0x134)
[<c025de30>] (vfs_read) from [<c025e720>] (SyS_read+0x4c/0xa4)
[<c025e720>] (SyS_read) from [<c01072c0>] (ret_fast_syscall+0x0/0x1c)

Change-Id: I09335112bed6efb30e60a22b471d4467eecaf520
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>