Chris Lattner [Thu, 12 Aug 2010 22:25:23 +0000 (22:25 +0000)]
fix PR7876: If ipsccp decides that a function's address is taken
before it rewrites the code, we need to use that in the post-rewrite pass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110962
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Bruno Cardoso Lopes [Thu, 12 Aug 2010 20:55:18 +0000 (20:55 +0000)]
Some small clean-up: use of pseudo instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110954
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Johnny Chen [Thu, 12 Aug 2010 20:46:17 +0000 (20:46 +0000)]
Cleaned up the for-disassembly-only entries in the arm instruction table so that
the memory barrier variants (other than 'SY' full system domain read and write)
are treated as one instruction with option operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110951
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Jakob Stoklund Olesen [Thu, 12 Aug 2010 20:38:03 +0000 (20:38 +0000)]
Also recompute HasPHIKill flags in LiveInterval::RenumberValues.
If a phi-def value were removed from the interval, the phi-kill flags are no
longer valid.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110949
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Evan Cheng [Thu, 12 Aug 2010 20:30:05 +0000 (20:30 +0000)]
Make sure ARM constant island pass does not break up an IT block. If the split point is in the middle of an IT block, it should move it up to just above the IT instruction. rdar://
8302637
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110947
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Bruno Cardoso Lopes [Thu, 12 Aug 2010 20:20:53 +0000 (20:20 +0000)]
- Teach SSEDomainFix to switch between different levels of AVX instructions. Here we guess that AVX will have domain issues, so just implement them for consistency and in the future we remove if it's unnecessary.
- Make foldMemoryOperandImpl aware of 256-bit zero vectors folding and support the 128-bit counterparts of AVX too.
- Make sure MOV[AU]PS instructions are only selected when SSE1 is enabled, and duplicate the patterns to match AVX.
- Add a testcase for a simple 128-bit zero vector creation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110946
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Jakob Stoklund Olesen [Thu, 12 Aug 2010 20:01:23 +0000 (20:01 +0000)]
Remove trailing whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110944
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Jakob Stoklund Olesen [Thu, 12 Aug 2010 18:50:55 +0000 (18:50 +0000)]
Clean up debug output.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110940
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Bruno Cardoso Lopes [Thu, 12 Aug 2010 18:20:59 +0000 (18:20 +0000)]
Define AVX 128-bit pattern versions of SET0PS/PD.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110937
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Bob Wilson [Thu, 12 Aug 2010 17:31:41 +0000 (17:31 +0000)]
Add a test for llvm-gcc svn 110632.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110935
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Jakob Stoklund Olesen [Thu, 12 Aug 2010 17:07:14 +0000 (17:07 +0000)]
Implement single block splitting.
Before spilling a live range, we split it into a separate range for each basic
block where it is used. That way we only get one reload per basic block if the
new smaller ranges can allocate to a register.
This type of splitting is already present in the standard spiller.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110934
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Dan Gohman [Thu, 12 Aug 2010 15:00:23 +0000 (15:00 +0000)]
Optimize ScalarEvolution::getAddExpr's operand factoring code by
having it finish processing all of the muliply operands before
starting the whole getAddExpr process over again, instead of
immediately after the first simplification.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110916
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Dan Gohman [Thu, 12 Aug 2010 14:52:55 +0000 (14:52 +0000)]
Hoist some loop-invariant code out of a hot loop.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110915
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Dan Gohman [Thu, 12 Aug 2010 14:46:54 +0000 (14:46 +0000)]
Optimize ScalarEvolution::getAddExpr's duplicate operand detection
by having it finish processing the whole operand list before
starting the whole getAddExpr process over again, instead of
immediately after the first duplicate is found.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110914
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Duncan Sands [Thu, 12 Aug 2010 11:31:39 +0000 (11:31 +0000)]
Add a 'normalize' method to the Triple class, which takes a mucked up
target triple and straightens it out. This does less than gcc's script
config.sub, for example it turns i386-mingw32 into i386--mingw32 not
i386-pc-mingw32, but it does a decent job of turning funky triples into
something that the rest of the Triple class can understand. The plan
is to use this to canonicalize triple's when they are first provided
by users, and have the rest of LLVM only deal with canonical triples.
Once this is done the special case workarounds in the Triple constructor
can be removed, making the class more regular and easier to use. The
comments and unittests for the Triple class are already adjusted in this
patch appropriately for this brave new world of increased uniformity.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110909
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Eric Christopher [Thu, 12 Aug 2010 07:01:22 +0000 (07:01 +0000)]
Temporarily revert 110737 and 110734, they were causing failures
in an external testsuite.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110905
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Bruno Cardoso Lopes [Thu, 12 Aug 2010 02:08:52 +0000 (02:08 +0000)]
Fix comment order
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110898
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Bruno Cardoso Lopes [Thu, 12 Aug 2010 02:06:36 +0000 (02:06 +0000)]
Begin to support some vector operations for AVX 256-bit intructions. The long
term goal here is to be able to match enough of vector_shuffle and build_vector
so all avx intrinsics which aren't mapped to their own built-ins but to
shufflevector calls can be codegen'd. This is the first (baby) step, support
building zeroed vectors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110897
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Johnny Chen [Thu, 12 Aug 2010 01:40:54 +0000 (01:40 +0000)]
The autogened decoder was confusing the ARM STRBT for ARM USAT, because the .td
entry for ARM STRBT is actually a super-instruction for A8.6.199 STRBT A1 & A2.
Recover by looking for ARM:USAT encoding pattern before delegating to the auto-
gened decoder.
Added a "usat" test case to arm-tests.txt.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110894
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Daniel Dunbar [Thu, 12 Aug 2010 00:55:42 +0000 (00:55 +0000)]
MC/X86/AsmParser: Give an explicit error message when we reject an instruction
because it could have an ambiguous suffix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110890
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Daniel Dunbar [Thu, 12 Aug 2010 00:55:38 +0000 (00:55 +0000)]
MC/AsmParser: Push the burdon of emitting diagnostics about unmatched
instructions onto the target specific parser, which can do a better job.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110889
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Daniel Dunbar [Thu, 12 Aug 2010 00:55:32 +0000 (00:55 +0000)]
tblgen/AsmMatcher: Always emit the match function as 'MatchInstructionImpl',
target specific parsers can adapt the TargetAsmParser to this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110888
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Devang Patel [Thu, 12 Aug 2010 00:17:38 +0000 (00:17 +0000)]
This is x86 only test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110887
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Daniel Dunbar [Wed, 11 Aug 2010 23:53:59 +0000 (23:53 +0000)]
configure: Add detection of the linker version string.
- Review appreciated, as long as you understand that I understand that this is
a horrible hack.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110883
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Johnny Chen [Wed, 11 Aug 2010 23:35:12 +0000 (23:35 +0000)]
Changed the format of DMBsy, DSBsy, and friends from Pseudo to MiscFrm.
Added two test cases to arm-tests.txt.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110880
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Devang Patel [Wed, 11 Aug 2010 23:17:54 +0000 (23:17 +0000)]
Even if a variable has constant value all the time, it is still a variable in gdb's eyes.
Tested by scope.exp in gdb testsuite.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110876
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Bob Wilson [Wed, 11 Aug 2010 23:10:46 +0000 (23:10 +0000)]
Move the ARM SSAT and USAT optional shift amount operand out of the
instruction opcode. This also fixes part of PR7792.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110875
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Jakob Stoklund Olesen [Wed, 11 Aug 2010 23:08:22 +0000 (23:08 +0000)]
Fix <rdar://problem/
8282498> even if it doesn't reproduce on trunk.
When a register is defined by a partial load:
%reg1234:sub_32 = MOV32mr <fi#-1>; GR64:%reg1234
That load cannot be folded into an instruction using the full 64-bit register.
It would become a 64-bit load.
This is related to the recent change to have isLoadFromStackSlot return false on
a sub-register load.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110874
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Owen Anderson [Wed, 11 Aug 2010 22:36:04 +0000 (22:36 +0000)]
Fix a subtle use-after-free issue.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110863
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Nick Lewycky [Wed, 11 Aug 2010 22:04:36 +0000 (22:04 +0000)]
Clean up ConstantRange a bit:
- remove ashr which never worked.
- fix lshr and shl and add tests.
- remove dead function "intersect1Wrapped".
- add a new sub method to subtract ranges, with test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110861
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Bruno Cardoso Lopes [Wed, 11 Aug 2010 21:12:09 +0000 (21:12 +0000)]
Add testcases for all AVX 256-bit intrinsics added in the last couple days
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110854
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Dan Gohman [Wed, 11 Aug 2010 20:34:43 +0000 (20:34 +0000)]
Make LoopPass::getContainedPass return a LoopPass* instead of a Pass*
and remove casts from all its callers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110848
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Dan Gohman [Wed, 11 Aug 2010 20:28:16 +0000 (20:28 +0000)]
Remove BasicBlockPass::runOnFunction, which was unused.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110847
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Bruno Cardoso Lopes [Wed, 11 Aug 2010 19:21:05 +0000 (19:21 +0000)]
Remove rsqrt/sqrt_nr intrinsics since there are no more builtins for them on clang
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110845
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Dan Gohman [Wed, 11 Aug 2010 19:11:05 +0000 (19:11 +0000)]
Delete FunctionPass::run, which is unused.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110843
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Dan Gohman [Wed, 11 Aug 2010 19:05:53 +0000 (19:05 +0000)]
Delete FunctionPass::runOnModule, which is unused.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110842
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Dan Gohman [Wed, 11 Aug 2010 18:15:01 +0000 (18:15 +0000)]
Don't use unsigned char for alignments in TargetData. There aren't
that many of these things, so the memory savings isn't significant,
and there are now situations where there can be alignments greater
than 128.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110836
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Dan Gohman [Wed, 11 Aug 2010 18:14:00 +0000 (18:14 +0000)]
Use ISD::ADD instead of ISD::SUB with a negated constant. This
avoids trouble if the return type of TD->getPointerSize() is
changed to something which doesn't promote to a signed type,
and is simpler anyway.
Also, use getCopyFromReg instead of getRegister to read a
physical register's value.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110835
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Bruno Cardoso Lopes [Wed, 11 Aug 2010 17:39:23 +0000 (17:39 +0000)]
Reapply r109881 using a more strict command line for llc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110833
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Jim Grosbach [Wed, 11 Aug 2010 17:32:46 +0000 (17:32 +0000)]
fix silly typo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110831
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Jim Grosbach [Wed, 11 Aug 2010 17:31:12 +0000 (17:31 +0000)]
Add a target triple, as the runtime library invocation varies a bit by
platform. It's apparently "bl __muldf3" on linux, for example. Since that's
not what we're checking here, it's more robust to just force a triple. We
just wwant to check that the inline FP instructions are only generated
on cpus that have them."
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110830
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Evan Cheng [Wed, 11 Aug 2010 17:25:51 +0000 (17:25 +0000)]
Fix test and re-enable it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110829
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Jakob Stoklund Olesen [Wed, 11 Aug 2010 16:50:17 +0000 (16:50 +0000)]
Fix a FIXME. The SlotIndex::Slot enum should be private.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110826
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Dan Gohman [Wed, 11 Aug 2010 16:36:07 +0000 (16:36 +0000)]
Temporarily disable some failing tests, until they can be
properly investigated.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110825
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Jim Grosbach [Wed, 11 Aug 2010 15:44:15 +0000 (15:44 +0000)]
cortex m4 has floating point support, but only single precision.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110810
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Dan Gohman [Wed, 11 Aug 2010 15:09:00 +0000 (15:09 +0000)]
Temporarily disable some failing tests, until they can be
properly investigated.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110808
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Bill Wendling [Wed, 11 Aug 2010 08:43:16 +0000 (08:43 +0000)]
Consider this code snippet:
float t1(int argc) {
return (argc == 1123) ? 1.234f : 2.38213f;
}
We would generate truly awful code on ARM (those with a weak stomach should look
away):
_t1:
movw r1, #1123
movs r2, #1
movs r3, #0
cmp r0, r1
mov.w r0, #0
it eq
moveq r0, r2
movs r1, #4
cmp r0, #0
it ne
movne r3, r1
adr r0, #LCPI1_0
ldr r0, [r0, r3]
bx lr
The problem was that legalization was creating a cascade of SELECT_CC nodes, for
for the comparison of "argc == 1123" which was fed into a SELECT node for the ?:
statement which was itself converted to a SELECT_CC node. This is because the
ARM back-end doesn't have custom lowering for SELECT nodes, so it used the
default "Expand".
I added a fairly simple "LowerSELECT" to the ARM back-end. It takes care of this
testcase, but can obviously be expanded to include more cases.
Now we generate this, which looks optimal to me:
_t1:
movw r1, #1123
movs r2, #0
cmp r0, r1
adr r0, #LCPI0_0
it eq
moveq r2, #4
ldr r0, [r0, r2]
bx lr
.align 2
LCPI0_0:
.long
1075344593 @ float 2.
382130e+00
.long
1067316150 @ float 1.
234000e+00
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110799
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Evan Cheng [Wed, 11 Aug 2010 07:17:46 +0000 (07:17 +0000)]
Report error if codegen tries to instantiate a ARM target when the cpu does support it. e.g. cortex-m* processors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110798
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Evan Cheng [Wed, 11 Aug 2010 07:00:16 +0000 (07:00 +0000)]
ArchV7M implies HW division instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110797
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Evan Cheng [Wed, 11 Aug 2010 06:57:53 +0000 (06:57 +0000)]
ArchV6T2, V7A, and V7M implies Thumb2; Archv7A implies NEON.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110796
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Evan Cheng [Wed, 11 Aug 2010 06:51:54 +0000 (06:51 +0000)]
Add ARM Archv6M and let it implies FeatureDB (having dmb, etc.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110795
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Daniel Dunbar [Wed, 11 Aug 2010 06:37:20 +0000 (06:37 +0000)]
MC/ARM: Add basic support for handling predication by parsing it out of the mnemonic into a separate operand form.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110794
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Daniel Dunbar [Wed, 11 Aug 2010 06:37:16 +0000 (06:37 +0000)]
MC/ARM: Split mnemonic on '.' characters.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110793
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Daniel Dunbar [Wed, 11 Aug 2010 06:37:12 +0000 (06:37 +0000)]
MC/ARM: Fill in ARMOperand::dump a bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110792
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Daniel Dunbar [Wed, 11 Aug 2010 06:37:09 +0000 (06:37 +0000)]
llvm-mc: Add -show-inst-operands, for dumping the parsed instruction representation before matching.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110791
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Daniel Dunbar [Wed, 11 Aug 2010 06:37:04 +0000 (06:37 +0000)]
MCAsmParser: Add dump() hook to MCParsedAsmOperand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110790
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Daniel Dunbar [Wed, 11 Aug 2010 06:36:59 +0000 (06:36 +0000)]
tblgen/AsmMatcher: Treat '.' in assembly strings as a token separator.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110789
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Daniel Dunbar [Wed, 11 Aug 2010 06:36:53 +0000 (06:36 +0000)]
MC/ARM: Add an ARMOperand class for condition codes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110788
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Evan Cheng [Wed, 11 Aug 2010 06:36:31 +0000 (06:36 +0000)]
Really control isel of barrier instructions with cpu feature.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110787
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Evan Cheng [Wed, 11 Aug 2010 06:30:38 +0000 (06:30 +0000)]
Add Cortex-M0 support. It's a ARMv6m device (no ARM mode) with some 32-bit
instructions: dmb, dsb, isb, msr, and mrs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110786
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Evan Cheng [Wed, 11 Aug 2010 06:22:01 +0000 (06:22 +0000)]
- Add subtarget feature -mattr=+db which determine whether an ARM cpu has the
memory and synchronization barrier dmb and dsb instructions.
- Change instruction names to something more sensible (matching name of actual
instructions).
- Added tests for memory barrier codegen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110785
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Daniel Dunbar [Wed, 11 Aug 2010 05:24:50 +0000 (05:24 +0000)]
MC/ARM: Switch to using the generated match functions instead of stub implementations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110783
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Daniel Dunbar [Wed, 11 Aug 2010 05:09:20 +0000 (05:09 +0000)]
MC/ARM: Enable generation of the ARM asm matcher, not that it can do much.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110782
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Daniel Dunbar [Wed, 11 Aug 2010 04:46:13 +0000 (04:46 +0000)]
ARM: Mark some disassembler only instructions as not available for matching --
for some reason they have a very odd MCInst form where the operands overlap, but
I haven't dug in to find out why yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110781
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Daniel Dunbar [Wed, 11 Aug 2010 04:46:10 +0000 (04:46 +0000)]
ARM: Quote $p in an asm string.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110780
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Daniel Dunbar [Wed, 11 Aug 2010 04:46:08 +0000 (04:46 +0000)]
tblgen/AsmMatcher: Downgrade instructions with tied operands to a debug-only warning, for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110779
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Owen Anderson [Wed, 11 Aug 2010 04:24:25 +0000 (04:24 +0000)]
Improve indentation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110778
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Bruno Cardoso Lopes [Wed, 11 Aug 2010 02:15:33 +0000 (02:15 +0000)]
Remove AVX 256-bit cast intrinsics now that clang is using __builtin_shufflevector for those
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110772
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Bruno Cardoso Lopes [Wed, 11 Aug 2010 01:44:11 +0000 (01:44 +0000)]
Remove AVX 256-bit unpack and interleave intrinsics now that clang is using __builtin_shufflevector for those
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110769
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Bruno Cardoso Lopes [Wed, 11 Aug 2010 01:18:26 +0000 (01:18 +0000)]
Remove AVX 256-bit shuffle intrinsics now that clang is using __builtin_shufflevector for those
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110767
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Bill Wendling [Wed, 11 Aug 2010 01:05:02 +0000 (01:05 +0000)]
Update test to match output of optimize compares for ARM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110765
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Oscar Fuentes [Wed, 11 Aug 2010 00:51:32 +0000 (00:51 +0000)]
CMake: corrections on LLVM.cmake external services.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110763
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Bill Wendling [Wed, 11 Aug 2010 00:23:00 +0000 (00:23 +0000)]
Handle ARM compares as well as converting for ARM adds, subs, and thumb2's adds.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110762
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Bill Wendling [Wed, 11 Aug 2010 00:22:27 +0000 (00:22 +0000)]
Mark ARM compare instructions as isCompare.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110761
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Rafael Espindola [Wed, 11 Aug 2010 00:15:13 +0000 (00:15 +0000)]
Make it possible to set the cpu used for codegen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110759
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Dan Gohman [Wed, 11 Aug 2010 00:12:36 +0000 (00:12 +0000)]
When analyzing loop exit conditions combined with and and or, don't
make any assumptions about when the two conditions will agree on when
to permit the loop to exit. This fixes PR7845.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110758
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Daniel Dunbar [Wed, 11 Aug 2010 00:11:19 +0000 (00:11 +0000)]
lto: Fix an inverted conditional which prevented the addition of symbols scraped
from inline assembly, except in cases where they had already been seen (in which
case they would get added twice).
- I can't see how this ever worked...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110757
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Daniel Dunbar [Wed, 11 Aug 2010 00:11:17 +0000 (00:11 +0000)]
lto: Fix gratuitous memory leaks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110756
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Bob Wilson [Wed, 11 Aug 2010 00:01:18 +0000 (00:01 +0000)]
Add a separate ARM instruction format for Saturate instructions.
(I discovered 2 more copies of the ARM instruction format list, bringing the
total to 4!! Two of them were already out of sync. I haven't yet gotten into
the disassembler enough to know the best way to fix this, but something needs
to be done.) Add support for encoding these instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110754
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Oscar Fuentes [Tue, 10 Aug 2010 23:48:22 +0000 (23:48 +0000)]
Avoid multiple definition warnings when both config.h and
llvm-config.h are included.
This is the cmake counterpart of r110547. See bug #7809.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110753
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Daniel Dunbar [Tue, 10 Aug 2010 23:46:46 +0000 (23:46 +0000)]
lto: Reduce nesting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110752
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Daniel Dunbar [Tue, 10 Aug 2010 23:46:39 +0000 (23:46 +0000)]
LTOModule.cpp: Fix numerous style issues.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110751
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Dan Gohman [Tue, 10 Aug 2010 23:46:30 +0000 (23:46 +0000)]
Rename and reorder the arguments to isImpliedCond, for consistency and clarity.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110750
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Eric Christopher [Tue, 10 Aug 2010 23:46:20 +0000 (23:46 +0000)]
We already have this as OperandNode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110748
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Evan Cheng [Tue, 10 Aug 2010 23:27:11 +0000 (23:27 +0000)]
CBZ and CBNZ are implemented.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110745
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Bruno Cardoso Lopes [Tue, 10 Aug 2010 23:25:42 +0000 (23:25 +0000)]
Add AVX matching patterns to Packed Bit Test intrinsics.
Apply the same approach of SSE4.1 ptest intrinsics but
create a new x86 node "testp" since AVX introduces
vtest{ps}{pd} instructions which set ZF and CF depending
on sign bit AND and ANDN of packed floating-point sources.
This is slightly different from what the "ptest" does.
Tests comming with the other 256 intrinsics tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110744
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Owen Anderson [Tue, 10 Aug 2010 23:20:01 +0000 (23:20 +0000)]
Now that we're using ConstantRange to represent potential values, make use of that represenation to
create constraints from comparisons other than eq/neq.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110742
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Bill Wendling [Tue, 10 Aug 2010 22:16:05 +0000 (22:16 +0000)]
The optimize comparisons pass removes the "cmp" instruction this is checking for.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110739
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Nate Begeman [Tue, 10 Aug 2010 21:58:00 +0000 (21:58 +0000)]
Add test for recent instcombine vector shuffle enhancement
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110737
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Chris Lattner [Tue, 10 Aug 2010 21:45:38 +0000 (21:45 +0000)]
upgrade to use new intrinsics, patch by Dan Hipschman!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110735
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Nate Begeman [Tue, 10 Aug 2010 21:38:12 +0000 (21:38 +0000)]
Add the minimal amount of smarts necessary to instcombine of shufflevectors to recognize
patterns generated by clang for transpose of a matrix in generic vectors. This is made
of two parts:
1) Propagating vector extracts of hi/lo half into their users
2) Recognizing an insertion of even elements followed by the odd elements as an unpack.
Testcase to come, but this shrinks the # of shuffle instructions generated on x86 from ~40 to the minimal 8.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110734
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Bill Wendling [Tue, 10 Aug 2010 21:38:11 +0000 (21:38 +0000)]
Turn optimize compares back on with fix. We needed to test that a machine op was
a register before checking if it was defined.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110733
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Jakob Stoklund Olesen [Tue, 10 Aug 2010 21:16:16 +0000 (21:16 +0000)]
Give up on register class recalculation when the register is used with subreg
operands. We don't currently have a hook to provide "the largest super class of
A where all registers' getSubReg(subidx) is valid and in B".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110730
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Dan Gohman [Tue, 10 Aug 2010 20:49:33 +0000 (20:49 +0000)]
Revert r110718; it broke clang-i386-darwin9.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110726
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Jakob Stoklund Olesen [Tue, 10 Aug 2010 20:45:07 +0000 (20:45 +0000)]
Avoid editing the current live interval during remat.
The live interval may be used for a spill slot as well, and that spill slot
could be shared by split registers. We cannot shrink it, even if we know the
current register won't need the spill slot in that range.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110721
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Jakob Stoklund Olesen [Tue, 10 Aug 2010 20:45:01 +0000 (20:45 +0000)]
More debug spew
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110720
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Bill Wendling [Tue, 10 Aug 2010 20:23:02 +0000 (20:23 +0000)]
Turn optimize cmps on by default so that we can get some testing by the nightly
ARM testers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110718
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Devang Patel [Tue, 10 Aug 2010 20:22:49 +0000 (20:22 +0000)]
Add missing argument. CreateCompositeTypeEx() users, please verify.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110717
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Owen Anderson [Tue, 10 Aug 2010 20:03:09 +0000 (20:03 +0000)]
Switch over to using ConstantRange to track integral values.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110714
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Devang Patel [Tue, 10 Aug 2010 20:01:20 +0000 (20:01 +0000)]
Do not forget debug info for enums. Use named mdnode to keep track of these types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110712
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