clk: rockchip: rk3399: add 216M and 96M for armclkb and armclkl

support 216M/96M for armclkb and armclkl

Change-Id: I26bf94ab0b27863a438b52be29e1a3aa208fa6ff
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

ARM64: dts: rk3399: don't let VOP LIT first to select eDP device

The endpoint order would decide the priority of connector devices,
the higher the priority ranking.

For now eDP can't light up with VOP Lit, so we need to cut down
the priority that eDP in VOP Lit, and raise up the priority that
MIPI in VOP Lit.

Change-Id: Ide4e321f03cf7ad5080c6db7f9230962963a3eb8
Signed-off-by: Yakir Yang <ykk@rock-chips.com>

ARM64: dts: rk3399: gru: Let VOP Big first to select connector device

This is a hack way to let VOP Big to select eDP device when VOP
Big and Lit all enabled.

Change-Id: Ia2bc91ff903bbc7d00deed57aab315328ce54378
Signed-off-by: Yakir Yang <ykk@rock-chips.com>

clk: rockchip: rk3399: fix clk_cifout setting clk error

Fix a typo making the clk_cifout access a
wrong clk tree to handle its mux and div.

Change-Id: Ief20e684eadd10b75cf36120df16f13c7581d303
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

ARM64: dts: rk3399: gru: add backlight and eDP panel device nodes

Panel brightness is controller by EC, the AP just enable/disable the
backlight power through GPIO1_C1.

Change-Id: I46e1f3b5098159cb07f86ba203ef8cfa102dd385
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>

ARM64: dts: rk3399: chrome: enable eDP support

The RK3399 EVB board is using the LG LP097QX1-SPA1
9.7" 2048x1536 eDP panel.

Change-Id: I837b0a569605591756918b12f56dbaa0b1f3f8d4
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>

HACK: ARM64: dts: rockchip: Hack out PWM regulators on gru

Until we get PWM regulator solid, let's hack it out and just keep
whatever the firmware set for us.

Note that when the kernel boots it appears that it does some reparenting
of clocks and the PWM frequency actually changes.  ...but the voltage
seems OK ish.

Change-Id: I3be6ea4460f685e4a75a0f7f31f767f09b908442
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Reviewed-on: https://chrome-internal-review.googlesource.com/254650
Reviewed-by: Stephen Barber <smbarber@google.com>
Tested-by: Doug Anderson <dianders@google.com>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
(Fixes the typo)

ARM64: dts: rockchip: rk808: set the dvs2 gpio pull down

the hw default of the dvs2 is pull up which is not correct.
set the dvs2 gpio pull down.

Change-Id: I0d296cecc422456cb72630d5ce64a5c7e5dad283
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

HACK: clk: rockchip: rk3399: Mark the PWM clock as critical

Until we get all the magic PWM regulator stuff solved with Boris's
wonderful upstream patches, let's just hack the PWM clock to be critical
so it never turns off.  Nuff said.

Change-Id: I99660b0b188413eb08030a3ae87c045c338b30db
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Reviewed-on: https://chrome-internal-review.googlesource.com/254649
Reviewed-by: Stephen Barber <smbarber@google.com>
Tested-by: Doug Anderson <dianders@google.com>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
(Fixes the pclk_rkpwm_pmu into pmucru_critical_clock)

ARM64: rockchip_cros_defconfig: cleanup for defconfig

We should make sure the config generate from the savedefconfig.
Okay, anyway cleanup the config with run 'make ARCH=arm64 savedefconfig'.

Change-Id: Ia094322870d378183760e32b7177971342e48439
Signed-off-by: Caesar Wang <wxt@rock-chips.com>

ARM64: dts: rk3399: gru: enable GPU device node

Change-Id: I2edad7d66cf655cb96ac6c933fdece9734eda469
Signed-off-by: Yakir Yang <ykk@rock-chips.com>

ARM64: rockchip_cros_defconfig: enable GPIO BACKLIGHT

The eDP panel of Kevin board only have a AP GPIO to control
the backlight power, so we need to enable the GPIO backlight
type for it.

Change-Id: I939e1c658b56ee5d889af820985f9ffd46f50485
Signed-off-by: Yakir Yang <ykk@rock-chips.com>

dt-bindings: add Samsung LSN122DL01-C01 panel binding

The Samsung LSN122DL01-C01 is an 12.2" 2560x1600 (WQXGA) TFT-LCD
panel connected using eDP interfaces.

Change-Id: Ib5164763d18c5cffcc83b38715f559a4a0c02638
Signed-off-by: Yakir Yang <ykk@rock-chips.com>

drm/panel: simple: Add support for Samsung LSN122DL01-C01 2560x1600 panel

The Samsung LSN122DL01-C01 is an 12.2" 2560x1600 (WQXGA) TFT-LCD panel
connected using eDP interfaces.

Change-Id: I3c2208fc45b53b0fab328fcb9ba204f610a9f9f6
Signed-off-by: Yakir Yang <ykk@rock-chips.com>

ARM: dts: rk3366-tb: adjust tx & rx delayline for 1000BT ethernet

Change-Id: I4d5f7150178d8f6f7e78f9109e49c73956aefaee
Signed-off-by: roger <roger.chen@rock-chips.com>

ARM64: dts: rockchip: fixes the hw-tshut-polarity for rk3399

AFAIK, the hardware designed that TSHUT should be set the active high.

Since rk3399 evb designed the over-temperature protection pin is
connected to PMIC that active high vaild.
Also, as gru/kevin designed the over-temperature protection pin is
connected to EC control that active high to prevent leakage.

Change-Id: Ib7b15d115d2ea4e474918fc416dde273b040e740
Signed-off-by: Caesar Wang <wxt@rock-chips.com>

drm: rockchip: analogix_dp: update the comments about why need to hardcode VOP output mode

The hardware IC designed that VOP must output the RGB10 video format to
eDP contoller, and if eDP panel only support RGB8, then eDP contoller
should cut down the video data, not via VOP contoller, that's why we need
to hardcode the VOP output mode to RGA10 here.

Change-Id: I733eae8a5dda51c0288d8627ceffb39a2f804e62
Signed-off-by: Yakir Yang <ykk@rock-chips.com>

drm: rockchip: analogix_dp: correct the connector display color format and bpc

Rockchip VOP couldn't output YUV video format for eDP controller, so
when driver detect connector support YUV video format, we could hack
it down to RGB888.

Change-Id: Ia876bb49e772f85bef201af2b62dd558d6b99257
Signed-off-by: Yakir Yang <ykk@rock-chips.com>

drm/bridge: analogix_dp: introduce connector mode_valid callback to plat driver

It's helpful to expand the mode_valid callback to platform driver,
so they could valid the display mode or informations.

Change-Id: Icfd7593bd10c93fc9045acf04a8d0ed6336ffb85
Signed-off-by: Yakir Yang <ykk@rock-chips.com>

drm/rockchip: analogix_dp: make panel detect to an optional action

Some boards don't need to declare a panel device node, like the
display interface is DP monitors, so it's necessary to make the
panel detect to an optional action.

Change-Id: I0146e9f9fb2e35b5878ab114e8aa1df35ba4843d
Signed-off-by: Yakir Yang <ykk@rock-chips.com>

Revert "drm/bridge: analogix_dp: hardcode input video format to RGB10 for Rockchip platform"

On RK3399 EVB board, the LG panel only support RGB888. so with previous
changes, VOP would send the RGB10 video format to panel, and then panel
just display abnormally.

This reverts commit 144e62cef352d9670f09de3ac1da53ca6182835c.

Change-Id: I09a5ab0aa8758e87e8b7f2fc20fbbaa113fe1d33
Signed-off-by: Yakir Yang <ykk@rock-chips.com>

ARM64: dts: rockchip: Remove default sample phase from gru

It looks like the addition of default-sample-phase to the GRU dts is
what was causing my periodic boot failures.  After removing it I found
that I could get 25+ reboots with no failures.  Calling it good.

BUG=None
TEST=Reboot many times; see successful boot each time.

Change-Id: Id200957da9d9a2eb81ce63dcb57c4f0f5e94e72d
Signed-off-by: Douglas Anderson <dianders@chromium.org>

UPSTREAM: drm: prime: Honour O_RDWR during prime-handle-to-fd

Currently DRM_IOCTL_PRIME_HANDLE_TO_FD rejects all flags except
(DRM|O)_CLOEXEC making it difficult (maybe impossible) for userspace
to mmap() the resulting dma-buf even when this is supported by the
DRM driver.

It is trivial to relax the restriction and permit read/write access.
This is safe because the flags are seldom touched by drm; mostly they
are passed verbatim to dma_buf calls.

v3 (Tiago): removed unused flags variable from drm_prime_handle_to_fd_ioctl.

Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Thompson <daniel.thompson@linaro.org>
Signed-off-by: Tiago Vignatti <tiago.vignatti@intel.com>
Reviewed-by: Stéphane Marchesin <marcheu@chromium.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Link: http://patchwork.freedesktop.org/patch/msgid/1450820214-12509-2-git-send-email-tiago.vignatti@intel.com
(cherry picked from commit bfe981a0952880df43d08a050bf3ae44aaebd795)
Signed-off-by: Brian Norris <briannorris@chromium.org>
Change-Id: Ieb3c547b1a08bd9c90fe72e0a1df1757d100aa8e
Reviewed-on: https://chrome-internal-review.googlesource.com/255266
Tested-by: Brian Norris <briannorris@google.com>
Reviewed-by: Doug Anderson <dianders@google.com>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>

ARM64: dts: rk3399-tb: adjust tx & rx delayline for 1000BT ethernet

Change-Id: I36dfc4d1289e388c7a955f3ba0e7f974b39d28fd
Signed-off-by: roger <roger.chen@rock-chips.com>

thermal: rockchip: add the notes for better reading

To update the notes for keeping in mind that quickly in case
someone re-read this driver in the future.

Change-Id: Ic752ed1d6a818f21560befd981383e8b532dff36
Signed-off-by: Caesar Wang <wxt@rock-chips.com>

thermal: rockchip: add the interleave value setting

The interleave is between power down and start of conversion,
This patch adds to workaround ic time sync issue for control.

Change-Id: Ib9f28fd92bcecf8ddaa8a69d47ced87fef04e7c6
Signed-off-by: Rocky Hao <rocky.hao@rock-chips.com>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>

thermal: rockchip: Support RK3366 SoCs in the thermal driver

The RK3366 SoCs have two Temperature Sensors, channel 0 is for CPU
channel 1 is for GPU.

Change-Id: I71324c65e82804f52d464b986e1d86127f8dc040
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

ARM64: rockchip_cros_defconfig: enable /proc/config.gz

This helps to be absolutely sure of what CONFIG_* switches are enabled
for your build.

Change-Id: Ic1043d78b01502af9f5a2d4776672c66fc152f5c
Signed-off-by: Brian Norris <briannorris@chromium.org>
Reviewed-on: https://chrome-internal-review.googlesource.com/254936
Commit-Queue: Brian Norris <briannorris@google.com>
Tested-by: Brian Norris <briannorris@google.com>
Reviewed-by: Stephen Barber <smbarber@google.com>

ARM64: dts: rockchip: Force pp3300_disp regulator to stay on

Normally, the display regulator would be kept powered on by the
display/backlight driver, but we don't yet have a DT representation or
driver for this, as the PWM is controlled by the EC. Just force the
regulator on for now.

This wasn't needed on some boards yet, since they were forcing this
regulator "on." But for those where we might be controlling it, we need
this. (And it's harmless otherwise.)

This is necessary but not sufficient for getting UI up on my board.

Change-Id: I30650c178dd42d76542f8f2491e22d9bf548363e
Signed-off-by: Brian Norris <briannorris@chromium.org>
Reviewed-on: https://chrome-internal-review.googlesource.com/254935
Commit-Queue: Brian Norris <briannorris@google.com>
Tested-by: Brian Norris <briannorris@google.com>
Reviewed-by: Stephen Barber <smbarber@google.com>

ARM64: rockchip_cros_defcofnig: enable DA7219 manchine driver and codec

Change-Id: Iaf0f1f63b6f1b8f0e3f391b1d900b201d59b9660
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

ARM64: dts: gru: Add support machine driver for DA7219

Now, we can playback and capture via DA7219 machine driver call the
da7219_aad_jack_det (simple-card can not do this).

Change-Id: I8b1be189031f875b1c5328e9357115761a5f4da3
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

ASoC: rockchip: Add support machine driver for DA7219

The DA7219 only support headphone playback, we may not call the
da7219_aad_jack_det when we use the simple-card.

Therefore, the machine driver may be need to submit upstream.

Change-Id: Iecf53fa62fcaf43175bbbcd2b7c8b0d5c67655ac
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

clk: rockchip: rk3399: Add CLK_SET_RATE_PARENT for main VOP0

We recommend, VOP0 is the main screen, VOP1 is a sub screen,
only VOP0 is able to re-set parent (VPLL) rate.

Change-Id: If40f95ce18e73477df8f7f031013333a603d5eb2
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

clk: rockchip: rk3399: Modify dummy clock for VOP dclks

Because frac div need to more than 20 multiple between the numerator
and denominator, but we need to be fit many HDMI/DP freqs and may
bring serious jitter when the dclk_vopx below the dclk_vopx_frac.

Therefore, we can select dclk_vopx below the dclk_vopx_div directly.

Change-Id: If3d9051211f0b160a507f0942667796f043f4ec2
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

UPSTREAM: ASoC: da7219: Correct BCLK inversion for DSP DAI format mode

By default the device latches data on the falling edge of the
BCLK in DSP mode, whereas the expectation for normal BCLK is to
latch on the rising edge. This updates the driver to invert the
BCLK configuration for DSP mode, to align with expected behaviour.

Signed-off-by: Adam Thomson <Adam.Thomson.Opensource@diasemi.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
(cherry picked from commit 4acfa36be618eb8ac3aa39f473e7550710216435)

Change-Id: I646f6ec9fb377ce95d90d57c80dc05f13b6696f2
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

UPSTREAM: ASoC: da7219: Add regmap patch to support old silicon

Initial silicon did not have master bias enabled by default, unlike
later HW, so use regmap patch to align with newer defaults.

Signed-off-by: Adam Thomson <Adam.Thomson.Opensource@diasemi.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
(cherry picked from commit abd7c894fc41a9a674354e10ed6c55413e1db077)

Change-Id: I1b941c779320b58110b78c2c127bb08629c7a3fa
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

UPSTREAM: ASoC: da7219: Remove support for 32KHz PLL mode

PLL mode based on 32KHz master clock not supported in
AB silicon so remove support from the driver.

Signed-off-by: Adam Thomson <Adam.Thomson.Opensource@diasemi.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
(cherry picked from commit 501f72e9c5205b9d70d5d61e9b186ae7ba873f73)

Change-Id: Ie3e3388af33a74fca6bf60405e1b54b860b43f18
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

UPSTREAM: ASoC: da7219: Add support for 1.6V micbias level

HW can provide 1.6V micbias level as well the existing levels
already provided in the driver. This patch adds support for 1.6V
to the DT binding.

Signed-off-by: Adam Thomson <Adam.Thomson.Opensource@diasemi.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
(cherry picked from commit 0aed64c1766d354c819a13a57d8673adaf2266eb)

Change-Id: I714fb76154242aa6392143ebe8db20a7510b45a3
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

UPSTREAM: ASoC: da7219: Remove internal LDO features of codec

In AB silicon, the internal LDO is not supported so remove
DT and driver references to this (digital voltage direct from
'VDD' supply)

Signed-off-by: Adam Thomson <Adam.Thomson.Opensource@diasemi.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
(cherry picked from commit d8ef140dccc1645aa37a140ed7585458294210b8)

Change-Id: I540c28a7dd0994c5dd94889c2cc0f566f8fddb63
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

UPSTREAM: ASoC: da7219: Update REFERENCES reg default, in-line with HW

In current AB silicon, BIAS_EN field is enabled by default in the
REFERENCES register, so the regmap default value should reflect
this.

Signed-off-by: Adam Thomson <Adam.Thomson.Opensource@diasemi.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
(cherry picked from commit 9ff099790412cb46536efba02039b36d81300976)

Change-Id: I8eabb89f669e02c6bda6ecee0b4253367082a59f
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

UPSTREAM: ASoC: da7219: Disable regulators on probe() failure

If codec probe() function fails after supplies have been enabled
it should really tidy up and disable them again. This patch updates
the probe function to do just that.

Signed-off-by: Adam Thomson <Adam.Thomson.Opensource@diasemi.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
(cherry picked from commit 9069bf9bc839d97e07fe17c336eab095c1065cec)

Change-Id: I3eebc1ff3af1b4f07fd564cc5d054ab0d6c43ad0
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

UPSTREAM: ASoC: da7219: Fix Sidetone to work regardless of DAI capture

Previously Sidetone would operate only when capture to DAI was in
progress, due to DAPM path configuration. There is no reason why
this should not operate without DAI capture, so this patch updates
the DAPM path accordingly.

Signed-off-by: Adam Thomson <Adam.Thomson.Opensource@diasemi.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
(cherry picked from commit fdd50a8086422caa456b5f8abb631dda6c551744)

Change-Id: I167dfe2bf18d696a01b8261b0fb0bb7a7569ec21
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

UPSTREAM: ASoC: da7219: Use logical instead of bitwise OR for boolean expression

Signed-off-by: Axel Lin <axel.lin@ingics.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
(cherry picked from commit a737447d080929c54c664adc9c62eadab9e86d3e)

Change-Id: I7b41ffe3d8144b1d4fa43dbf13e324f2f8d409ad
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

dt/bindings: rockchip-thermal: Support the RK3366 SoCs compatible

This patchset attempts to new compatible for thermal founding
on RK3366 SoCs.

Change-Id: Ida2a46f0c8dfb8f9e99c8c7ba488be07dac8a5e8
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

ARM64: dts: rockchip: Change PWM regulators to 300kHz for gru base

Apparently the time constant for for the PWM regulator circuit on
gru-based devices is different than EVB.  Let's run at 300kHz which
should make us work well.

BUG=None
TEST=None

Change-Id: I0973f416d026de27908c3ef527c1e9274b967fc8
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Reviewed-on: https://chrome-internal-review.googlesource.com/254648
Reviewed-by: Stephen Barber <smbarber@google.com>
Tested-by: Doug Anderson <dianders@google.com>

video: rockchip: vop: 3399: enable auto gating

Change-Id: I78e1f2b0c90545f0bb9e33b98979f8c102b123b5
Signed-off-by: Huang Jiachai <hjc@rock-chips.com>

ARM64: dts: rk3399: add "rockchip,grf" for i2s0

Change-Id: I8f275e960db8fe180d769fd7f081a379f8ace1a2
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>

UPSTREAM: ASoC: rockchip: i2s: configure the sdio pins' iomux mode

There are 3 i2s sdio pins, which iomux mode is as follows:

 - sdi3_sdo1
 - sdi2_sdo2
 - sdi1_sdo3

we need to configure these pins' iomux mode via the GRF register
when use multi channel playback/capture.

Change-Id: I95f01f425931d8fb826f33d5dad87ef8aa2b8b6e
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
(cherry picked from git.kernel.org broonie/sound.git topic/rockchip
 commit 72b7ba1f1477f1b9b0a3ddf2dd4b5392ce88a8a3)

UPSTREAM: ASoC: rockchip: add playback property

rockchip,playback-channels: max playback channels, 8 channels default.

Change-Id: I0db92ad3d3270e46bb98a2977163869251c32f2d
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
(cherry picked from commit 7fd9093a7570f5d8bbdc8014c0a349da2afea97e)

clk: rockchip: rk3399: add softreset ID for gpu

Change-Id: I19613ee4a35f3a61c4f02f30449ce9e389bb7162
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

usb: dwc3: add functions to set force mode

Add functions to set force mode for host and device.
These functions will check the current mode and only
force if needed thus avoiding unnecessary force mode
delays. It's useful for dwc3 controller on some platforms
which don't support otg mode but support drd mode,
like rk3399 platform.

TEST=config dr_mode = "otg" in dts first, and do
"echo device > mode" on usb debugfs dir to force device mode,
do "echo host > mode" on usb debugfs dir to force host mode.

Change-Id: I1f90ac9d1ee3daa19c1046b0e52fdfb8f2d2ad62
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>

drm/panel: simple: Add support for LG LP097QX1-SPA1 2048x1536 panel

The LG LP097QX1-SPA1 is an 9.7", 2048x1536 (QXGA) TFT-LCD panel
connected using eDP interfaces.

Change-Id: I3a279ff9e4dde421832e2f9fe8152ddfbadab2ae
Signed-off-by: Yakir Yang <ykk@rock-chips.com>

dt-bindings: add LG LP097QX1-SPA1 panle binding

The LG LP097QX1-SPA1 is an 9.7", 2048x1536 (QXGA) TFT-LCD panel
connected using eDP interfaces.

Change-Id: I09554d0c2afcce744e959878c7cd9d9950b35a17
Signed-off-by: Yakir Yang <ykk@rock-chips.com>

ARM64: dts: rk3399: assign VOP parent and rate for ACLK/HCLK

Change-Id: Ifcce7764eb709386e40140c58299468ea835fd8c
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

UPSTREAM: [media] media/core: Replace ctrl_class with which

Replace the obsolete field ctrl_class with "which".

Make sure it not used in future modules by commenting out the field with
ifndef __KERNEL_ .

The field cannot be simply removed because that would be change on the
kenel API to the userspace (and we don't like that).

Change-Id: I21bfb7c2a4b553e74765213fd99c381d8b609cc0
Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com>
Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@osg.samsung.com>
Signed-off-by: Alpha Lin <alpha.lin@rock-chips.com>
(cherry picked from commit 0f8017bebf3efd3dcb115bf8a3f883b3123019ee)

UPSTREAM: [media] videodev2.h: Extend struct v4l2_ext_controls

So it can be used to get the default value of a control.

Without this change it is not possible to get the
default value of array controls.

Change-Id: I4370b7f2a40a08f28648f8dcaa3d84405db12523
Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com>
Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@osg.samsung.com>
Signed-off-by: Alpha Lin <alpha.lin@rock-chips.com>
(cherry picked from commit 35ec2a2fa5a362b07b590ae1568dc35e47a7b846)

video: rockchip: vop: 3399: fix win lite disp size error

Change-Id: I8874026dfd75353c129418a29d860499773e2ebb
Signed-off-by: Huang Jiachai <hjc@rock-chips.com>

video: rockchip: vop: 3399: update for dsp output mode

Change-Id: I3558b90bea9cdad7954d17004c08cfc2c2c53aa0
Signed-off-by: Huang Jiachai <hjc@rock-chips.com>

video: rockchip: vop: 3399: update for CABC

Change-Id: I6e93d0e8daedf8a1c671ebbc28719da0296083da
Signed-off-by: Huang Jiachai <hjc@rock-chips.com>

video: rockchip: vop: 3399: add property for hwc layer

Change-Id: I012603cb216419b41a79470ebc26c8525d6a7326
Signed-off-by: Huang Jiachai <hjc@rock-chips.com>

ARM64: dts: rk3399-fb: make sure vop big probe first

Change-Id: I16f966aeadbc6a97c128c0c750863495d0fa46c0
Signed-off-by: Huang Jiachai <hjc@rock-chips.com>

video: rockchip: vop: 3399: update for write back function

Change-Id: I5c0ceb6797211a1384de7174f158288209d03dd2
Signed-off-by: Huang Jiachai <hjc@rock-chips.com>

ARM64: dts: rk3399-monkey: add pstore node

Change-Id: Ie4e3a3c390807c5d0559eee3d0627a5dae2bd9b3
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>

ARM64: rockchip_defconfig: enable pstore

Change-Id: Ieda4ab0d02287c24c3c346ddefdbcf12c03eaf43
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>

net: stmmac: replace msleep with mdelay between spinlock and spinunlock

stmmac_mdio_reset()
{
...
msleep()
...
}

stmmac_resume()
{
...
spin_lock_irqsave()
...
stmmac_mdio_reset()
...
spin_unlock_irqrestore()
}

The code above will cause the following crash when resuming.

[   50.988242] Call trace:
[   50.988489] [<ffffffc0000883b0>] dump_backtrace+0x0/0x104
[   50.988979] [<ffffffc0000884c8>] show_stack+0x14/0x1c
[   50.989440] [<ffffffc0003033f8>] dump_stack+0x90/0xb0
[   50.989899] [<ffffffc0000bb4d4>] __schedule_bug+0x44/0x5c
[   50.990388] [<ffffffc000949d00>] __schedule+0x90/0x6d8
[   50.990851] [<ffffffc00094a44c>] schedule+0x90/0xb0
[   50.991295] [<ffffffc00094cdbc>] schedule_timeout+0x1f0/0x254
[   50.991812] [<ffffffc00094ce90>] schedule_timeout_uninterruptible+0x20/0x28
[   50.992437] [<ffffffc0000ef2ac>] msleep+0x18/0x24
[   50.992870] [<ffffffc0004b2fc0>] stmmac_mdio_reset+0x120/0x194
[   50.993397] [<ffffffc0004b1c40>] stmmac_resume+0x118/0x134
[   50.993893] [<ffffffc0004b64bc>] stmmac_pltfr_resume+0x30/0x3c
[   50.994421] [<ffffffc00045b44c>] platform_pm_resume+0x2c/0x54
[   50.994943] [<ffffffc000465350>] dpm_run_callback+0xa8/0x1e0
[   50.995452] [<ffffffc000465fd4>] device_resume+0x158/0x190
[   50.995945] [<ffffffc000466178>] dpm_resume+0x16c/0x364
[   50.996417] [<ffffffc000466384>] dpm_resume_end+0x14/0x28
[   50.996905] [<ffffffc0000d8bfc>] suspend_devices_and_enter+0x114/0x2f4
[   50.997489] [<ffffffc0000d93c8>] pm_suspend+0x5ec/0x658
[   50.997960] [<ffffffc0000d7748>] state_store+0x50/0x88
[   50.998427] [<ffffffc000305594>] kobj_attr_store+0x18/0x28
[   50.998926] [<ffffffc0001ec038>] sysfs_kf_write+0x44/0x4c
[   50.999414] [<ffffffc0001eb3f4>] kernfs_fop_write+0x110/0x16c
[   50.999935] [<ffffffc00018d208>] __vfs_write+0x28/0xd0
[   51.000400] [<ffffffc00018d464>] vfs_write+0xb0/0x180
[   51.000858] [<ffffffc00018d600>] SyS_write+0x48/0x84
[   51.001311] [<ffffffc0000844b0>] el0_svc_naked+0x24/0x28
[   51.066648] ERROR stmmaceth/eth0, debugfs create directory failed
[   51.067196] stmmac_hw_setup: failed debugFS registration

Change-Id: Iee92ac9bae18a6e8fb980434c7004dd33b43b638
Signed-off-by: roger <roger.chen@rock-chips.com>

ARM64: CrOS: defconfig: update defconfig for chromeos

The CONFIG_ANDROID_PARANOID_NETWORK will block network access on ChromeOS.
Disable it on CrOS.

CONFIG_DRM_DMA_SYNC can be used to synchronize CPU/GPU access to a buffer.

Change-Id: Ia979af42b8693161c854e1987122d49c8737b51c
Signed-off-by: ZhengShunQian <zhengsq@rock-chips.com>

CHROMIUM: drm/rockchip: add GEM CPU acquire/release ioctls

These ioctls can be used to synchronize CPU/GPU access to a buffer.

BUG=chrome-os-partner:33438
TEST=add CONFIG_DRM_DMA_SYNC=y, in conjunction with xf86-video-armsoc change,\
run any X application, like xev

Change-Id: I8065ec465ebd0cb6abe128a3e7d92a8f74a88928
Signed-off-by: Dominik Behr <dbehr@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/229441
Reviewed-by: Daniel Kurtz <djkurtz@chromium.org>
Conflicts:
drivers/gpu/drm/rockchip/rockchip_drm_drv.c
drivers/gpu/drm/rockchip/rockchip_drm_drv.h
drivers/gpu/drm/rockchip/rockchip_drm_gem.c
(cherry picked from cros/chromeos-3.14 commit a847e1f492cbd186116c01a3f56575320dc87152)
Signed-off-by: ZhengShunQian <zhengsq@rock-chips.com>

CHROMIUM: drm/rockchip: Add GEM create ioctl support

Rockchip Socs have GPU, we need allocate GPU accelerated buffers.
So add special ioctls GEM_CREATE/GEM_MAP_OFFSET to support
accelerated buffers.

Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
BUG=chromium:399935
TEST=With rest of patch set, can boot to UI on eDP

Change-Id: Ia4b13798aac97d16214da7a75a2479e6e334313e
Reviewed-on: https://chromium-review.googlesource.com/222153
Reviewed-by: Daniel Kurtz <djkurtz@chromium.org>
Tested-by: Daniel Kurtz <djkurtz@chromium.org>
Commit-Queue: Daniel Kurtz <djkurtz@chromium.org>
Conflicts:
drivers/gpu/drm/rockchip/rockchip_drm_drv.c
(cherry picked from cros/chromeos-3.14 commit c29c5a3037e18815937d8af664738e499ada94d1)
Signed-off-by: ZhengShunQian <zhengsq@rock-chips.com>

CHROMIUM: drm: add helpers for fence and reservation based dma-buf sync

BUG=chromium:395901
TEST=emerge-veyron chromeos-kernel-3_14, deploy and boot kernel

Change-Id: I0cdf6d23e9f4924128d4de77c0f3ed7589766bb8
Signed-off-by: Dominik Behr <dbehr@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/218381
Conflicts:
drivers/gpu/drm/Makefile
(cherry picked from cros/chromeos-3.14 commit 0adee464da8094c70469514dd96799c1797f77b0)
Signed-off-by: ZhengShunQian <zhengsq@rock-chips.com>

drm: rockchip: analogix_dp: split the lcdc select setting into device data

eDP controller need to declare which vop provide the video source,
and it's defined in GRF registers.

But the specific GRF register address is different between RK3288
and RK3399, so we need to create a device data to declare the GRF
messages for each CPU chips.

Change-Id: I695d1c729f5605d9e913c82453d311ed97c79a94
Signed-off-by: Yakir Yang <ykk@rock-chips.com>

clk: rockchip: rk3399: move VOP clock to other PLLs

We hope to be able to HDMI/DP can obtain better signal quality,
therefore, we move VOP pwm and aclk clocks to other PLLs, let
HDMI/DP phyclock can monopolize VPLL.

Change-Id: Ib715f9d29c0743d113f9f74886ff3921c9e0a327
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

ARM64: config: enable the REGULATOR_PWM for rockchip

That's useful for every PWM controlled to adjust the voltage
regulators.

In the moment. We make savedefconfig to cleanup the rockchuip_cros_defconfig.

Change-Id: I33d68d6cd48310b2da0ea2c3331380e71fc51eee
Signed-off-by: Caesar Wang <wxt@rock-chips.com>

ARM64: dts: gru: fix up the pwm regulator node

This attempts to model commit 063e65397a89 ("ARM64: dts: rk3399-tb: fix
up the pwm regulator node").

Note that instead of putting a duty cycle of 25000 ns (40 kHz) I've set
a duty cycle of 1667 ns (600 kHz) because I think that's what the TRM
says.

Change-Id: Ifc209eddb20122feec96c5e86f7a14da7d74eb3f
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>

ARM64: dts: rk3399-chrome: delete unused code in dts

We shouldn't need them in here if you are using the coreboot/firmware.
In general, the cmdline/memory/logic_center will be overwrited
since the coreboot will do that.

Change-Id: I3902ff4eb71891b5c6320bed4355992e699e4835
Signed-off-by: Caesar Wang <wxt@rock-chips.com>

ARM64: dts: rk3399-monkey: add iep dts resource for android

Add the iep dts resource for android platform.

Change-Id: Ibb624fe0ad5253fb026d3470b52f76bc61cdb960
Signed-off-by: alpha.lin <alpha.lin@rock-chips.com>

ARM64: dts: rk3399: gru: enable eDP display nodes

Change-Id: I1548fdebfb9bb3ac98e309a3becfa16216e94ede
Signed-off-by: Yakir Yang <ykk@rock-chips.com>

ARM64: dts: rk3399: remove aclk_usb3_noc which is ignored unused

Change-Id: Ie864933514db3f1117ea67bd06549ad145514bef
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>

clk: rockchip: rk3399: add SCLK_PCIEPHY_REF100M for PCIe

Change-Id: Iead548d47a627745267acbcc73d401f73c68a702
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

ARM64: dts: rk3399: add eDP device node

Change-Id: I0b1bb874b51f45d71f63445cb30c43f94b022c20
Signed-off-by: Yakir Yang <ykk@rock-chips.com>

drm/bridge: analogix_dp: hardcode input video format to RGB10 for Rockchip platform

Rockchip LCD controller could only output the RGB101010 video
format, so just hardcode the eDP input video format to that.

Change-Id: I39673a35b439656dff7e3358b65ec835c92c4120
Signed-off-by: Yakir Yang <ykk@rock-chips.com>

net: phy: add sysfs node for reading PHY's registers

Change-Id: I76468dd235a39b6f79699b1cc931c2c7bb7bdbc5
Signed-off-by: roger <roger.chen@rock-chips.com>

ARM64: dts: rk3399-tb: change "ext_gmac" to "clkin_gmac" according to clk-rk3399.c

Change-Id: Ic0ea696408493aae97099d579d34ae33f30cc41a
Signed-off-by: roger <roger.chen@rock-chips.com>

ARM64: dts: rk3399: fix drive strength to 13mA for GMAC TXD pins

Change-Id: Ia5a45864d2f71bd7548cc5b897c33265a20c4fea
Signed-off-by: roger <roger.chen@rock-chips.com>

clk: rockchip: rk3399: remove unnecessary CLK_IGNORE_UNUSED flags

remove unnecessary CLK_IGNORE_UNUSED flags for m0.

Change-Id: Iba9daf76980c969b90700c175bfa5fec044f3524
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

clk: rockchip: rk3399: remove unnecessary CLK_IGNORE_UNUSED flags

remove unnecessary CLK_IGNORE_UNUSED flags for uart4/gpio/timer.

Change-Id: I6046dd8d12cc78363d4e653bcad78671746a3914
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

ARM64: rockchip_defconfig: enable IPA and CPU_THERMAL

Change-Id: Ia70704b3e77041231f02246ad1a230a45d4b930f
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>

clk: rockchip: rk3399: add SCLK_RMII_SRC for gmac

Change-Id: I0b678b60ab99ba8166866a7f664314055f55c606
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

mfd: RK808: update the "pm_power_off" initalization conditons

Only the powerofff callback feature is supported through the
rockchip,system-power-controller.

Change-Id: I55e73c05a749edab6c3710e304ee86c03812ab6f
Signed-off-by: Shengfei xu <xsf@rock-chips.com>

include: drm: rockchip_drm.h: remove those old unsued file

Thoes file were introduced by Commit bdafdac384d56555736584775236dbd817a1cdda
(rk3288 chromium: drm grafic fb support for x11 mali gpu), for now we have the
mainline rockchip drm code, no need those old head files, let's removed them.

Change-Id: I325a5b7981ac5478349f276f8811b1b51e40c564
Signed-off-by: Yakir Yang <ykk@rock-chips.com>

video: rockchip: mipi: add long packet support for linux-4.4

Change-Id: I0f226f0caabe100c6c41c9b0b23f80a2c61f7f4f
Signed-off-by: xubilv <xbl@rock-chips.com>

ARM64: dts: gru: Put back in TODO comments + recent SD work

This DTS purposely has some comments in "//" style to indicate bringup
work that needs to be done.  Don't remove them unless the issues have
been addressed.

The DTS that landed in Rockchip's tree also lost some recent SD work.

Change-Id: I388cfe855b52aa160c1e8d1b468d7e8f35207790
Signed-off-by: Douglas Anderson <dianders@chromium.org>

ARM64: dts: rk3399-monkey: enable iommu and vop lite

Change-Id: I6cb75f09c99ffe76691ceb61d60774256663e72e
Signed-off-by: Huang Jiachai <hjc@rock-chips.com>

video: rockchip: vop: 3399: update hdmi RGB101010 output and csc parameter

Change-Id: I7428da925c78f68f418ff5669b08c8cfd44808b6
Signed-off-by: Huang Jiachai <hjc@rock-chips.com>

video: rockchip: vop: 3399: update for iommu

Change-Id: Ic4550a2534fd016b6fff7e47f8d89ec239beba10
Signed-off-by: Huang Jiachai <hjc@rock-chips.com>

video: rockchip: rk322x: check hwc_size before H/W register config

Check hwc_size after hwc registor config, if check fail, would cause
unexpect problem, iommu crash.

Change-Id: I2e18ea86e9e27e13ccce0737d9d48befcbe345fb
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>

video: rockchip: vop: 3399: add win2 and win3 when get dsp_info

Change-Id: Ib1ae76de66656b0531683eede117346945587008
Signed-off-by: Huang Jiachai <hjc@rock-chips.com>

video: rockchip: vop: 3399: add to config YUYV and UYVY data format

Change-Id: I5762f691d724449035098333a732095774c96513
Signed-off-by: Huang Jiachai <hjc@rock-chips.com>

video: rockchip: fb: add support data format YUYV and UYVY

Change-Id: Iaef1a0e6f80e4246cfe6b2692bdb6085ea5355b0
Signed-off-by: Huang Jiachai <hjc@rock-chips.com>

video: rockchip: vop: 3399: add support afbdc

Change-Id: I2e796809baeef99c3463c4789a65eb1057cb577f
Signed-off-by: Huang Jiachai <hjc@rock-chips.com>

thermal: rockchip: fixes the code_to_temp for tsadc driver

We should judge the table.id[mid].code insearch algorithm on matter the
adc value increment or decrement.

Or otherwise, the temperature return the incorrect value in some cases.
[    1.438589] adc_val=402,temp=-40000
[    1.438903] adc_val=403,temp=-39375
[    1.439217] adc_val=404,temp=-38750
...
[    1.441102] adc_val=410,temp=-40000
[    1.441416] adc_val=411,temp=-34445
[    1.441737] adc_val=412,temp=-33889
...

Let's fix it right now.

Fixes commit 020ba95
"thermal: rockchip: Add the sort mode for adc value increment or decrement"

Change-Id: Icac84d06ebf463439ca11db5a19d629b4b2b865c
Reported-by: Rocky Hao <rocky.hao@rock-chips.com>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>