Keep VC++ happy.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24835 91177308-0d34-0410-b5e6-96231b3b80d8

This is handled by the autogen'd code

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24834 91177308-0d34-0410-b5e6-96231b3b80d8

Handle basic block nodes

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24833 91177308-0d34-0410-b5e6-96231b3b80d8

Change return lowering so that we can autogen the matching code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24832 91177308-0d34-0410-b5e6-96231b3b80d8

Add an accessor

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24831 91177308-0d34-0410-b5e6-96231b3b80d8

Implement Calls for V8.  This would be completely autogenerated except for
a small bug in tblgen.  When that is fixed, we can remove the ISD::Call case
in Select.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24830 91177308-0d34-0410-b5e6-96231b3b80d8

More fixes for Selection of copyto/fromreg with a flag

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24829 91177308-0d34-0410-b5e6-96231b3b80d8

More corrections for flagged copyto/from reg

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24828 91177308-0d34-0410-b5e6-96231b3b80d8

Select copytoreg and copyfromreg nodes that have flag operands correctly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24827 91177308-0d34-0410-b5e6-96231b3b80d8

legalize copytoreg and copyfromreg nodes that have flag operands correctly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24826 91177308-0d34-0410-b5e6-96231b3b80d8

Implement the full V8 ABI for incoming arguments.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24825 91177308-0d34-0410-b5e6-96231b3b80d8

Push ops list, asm string, and pattern all the way up to InstV8.  Move the
InstV8 class to the InstrFormats file where it belongs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24824 91177308-0d34-0410-b5e6-96231b3b80d8

Give V8 select_cc, in the spirit of the PPC backend

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24823 91177308-0d34-0410-b5e6-96231b3b80d8

remove some unused instructions

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24822 91177308-0d34-0410-b5e6-96231b3b80d8

V8 doesn't have FP extload

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24821 91177308-0d34-0410-b5e6-96231b3b80d8

simplifications, fix typo

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24820 91177308-0d34-0410-b5e6-96231b3b80d8

add a node, for completeness

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24819 91177308-0d34-0410-b5e6-96231b3b80d8

Add frameindex support
Add support for copying (e.g. returning) doubles
Add support for F<->I instructions

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24818 91177308-0d34-0410-b5e6-96231b3b80d8

Tighten up some checks

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24817 91177308-0d34-0410-b5e6-96231b3b80d8

Fix a bug Sabre was having where the DAG root was a group.  The group dominator
needed to be added to the ordering list, not the first member of the group.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24816 91177308-0d34-0410-b5e6-96231b3b80d8

Groups were not emitted if the dominator node and the node in the ordering list
were not the same node.  Ultimately the test was bogus.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24815 91177308-0d34-0410-b5e6-96231b3b80d8

Since extload can also be used by FP, split STDIntExtLoad into two parts,
one for use with extload, one for use with sextload and zextload, which
are integer only.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24814 91177308-0d34-0410-b5e6-96231b3b80d8

Add constant pool support, including folding into addresses.
Pretty print addresses a bit, to not print [%r1+%g0]: just print [%r1]

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24813 91177308-0d34-0410-b5e6-96231b3b80d8

Teach the addressing mode stuff to fold "%lo" into 'ri' addressing modes,
allowing us to compile this:

to this:

%G1 = external global int
%G2 = external global int
void %test() {
        %X = load int* %G1
        store int %X, int* %G2
        ret void
}

test:
        save -96, %sp, %sp
        sethi %hi(G1), %l0
        ld [%l0+%lo(G1)], %l0
        sethi %hi(G2), %l1
        st %l0, [%l1+%lo(G2)]
        restore %g0, %g0, %g0
        retl
        nop

instead of this:

test:
        save -96, %sp, %sp
        sethi %hi(G1), %l0
        or %g0, %lo(G1), %l1
        ld [%l1+%l0], %l0
        sethi %hi(G2), %l1
        or %g0, %lo(G2), %l2
        st %l0, [%l2+%l1]
        restore %g0, %g0, %g0
        retl
        nop

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24812 91177308-0d34-0410-b5e6-96231b3b80d8

Add initial support for global variables, and fix a bug in addr mode selection
where we didn't select the operands.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24811 91177308-0d34-0410-b5e6-96231b3b80d8

Claiming that branch targets are registers is not very wholesome.  Change them
to be basic blocks.  Also, add uncond branches.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24810 91177308-0d34-0410-b5e6-96231b3b80d8

Add unordered comparisons

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24809 91177308-0d34-0410-b5e6-96231b3b80d8

Add patterns to the rest of the int condbranches and some of the fp branches

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24808 91177308-0d34-0410-b5e6-96231b3b80d8

Add initial conditional branch support.  This doesn't actually work yet due
to a bug in the scheduler.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24807 91177308-0d34-0410-b5e6-96231b3b80d8

Simplify code

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24806 91177308-0d34-0410-b5e6-96231b3b80d8

Eliminate CMPri, which is a synonym for SUBCCri

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24805 91177308-0d34-0410-b5e6-96231b3b80d8

allow custom expansion of BR_CC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24804 91177308-0d34-0410-b5e6-96231b3b80d8

add fneg,fabs,fsqrt instructions

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24803 91177308-0d34-0410-b5e6-96231b3b80d8

Add patterns for fround/fextend and the funny fsmuld instruction

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24802 91177308-0d34-0410-b5e6-96231b3b80d8

Add FP +,-,*,/

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24801 91177308-0d34-0410-b5e6-96231b3b80d8

Give patterns to F3_3 instructions

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24800 91177308-0d34-0410-b5e6-96231b3b80d8

Implement 64-bit add/sub, make sure to receive and return 64-bit args with
the right halves in the right regs

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24799 91177308-0d34-0410-b5e6-96231b3b80d8

implement div and rem

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24798 91177308-0d34-0410-b5e6-96231b3b80d8

implement MULHU/MULHS for 64-bit multiplies

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24797 91177308-0d34-0410-b5e6-96231b3b80d8

Add patterns for multiply, simplify Y register handling stuff, add RDY instruction

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24796 91177308-0d34-0410-b5e6-96231b3b80d8

Make the addressing modes smarter

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24795 91177308-0d34-0410-b5e6-96231b3b80d8

remove some unused instructions

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24794 91177308-0d34-0410-b5e6-96231b3b80d8

add andn/orn/xorn patterns.  This allows us to compile this:

long %test(ubyte, short, long %X, long %Y) {
  %A = xor long %X, -1
  %B = and long %Y, %A
  ret long %B
}

to this:

test:
        save -96, %sp, %sp
        andn %i4, %i2, %i0
        andn %i5, %i3, %i1
        restore %g0, %g0, %g0
        retl
        nop

instead of this:

test:
        save -96, %sp, %sp
        xor %i2, -1, %l0
        xor %i3, -1, %l1
        and %i4, %l0, %i0
        and %i5, %l1, %i1
        restore %g0, %g0, %g0
        retl
        nop

The simpleisel emits:  :(

test:
        save -96, %sp, %sp
        or %g0, -1, %l0
        or %g0, -1, %l0
        or %g0, -1, %l0
        or %g0, -1, %l1
        xor %i2, %l0, %l0
        xor %i3, %l1, %l1
        and %i4, %l0, %i0
        and %i5, %l1, %i1
        restore %g0, %g0, %g0
        retl
        nop

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24793 91177308-0d34-0410-b5e6-96231b3b80d8

Add support for 64-bit arguments

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24792 91177308-0d34-0410-b5e6-96231b3b80d8

Sparc doesn't have sext_inreg

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24791 91177308-0d34-0410-b5e6-96231b3b80d8

add patterns for FP stores

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24790 91177308-0d34-0410-b5e6-96231b3b80d8

Add [reg+reg] integer stores

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24789 91177308-0d34-0410-b5e6-96231b3b80d8

Add store patterns

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24788 91177308-0d34-0410-b5e6-96231b3b80d8

add truncstore

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24787 91177308-0d34-0410-b5e6-96231b3b80d8

add fp load patterns, switch rest of loads and stores to use addrmodes

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24786 91177308-0d34-0410-b5e6-96231b3b80d8

Add integer load[r+r] forms.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24785 91177308-0d34-0410-b5e6-96231b3b80d8

Rename load/store instructions to include an RI suffix

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24784 91177308-0d34-0410-b5e6-96231b3b80d8

Add patterns for the rest of the loads.  Add 'ri' suffixes to the load and store insts

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24783 91177308-0d34-0410-b5e6-96231b3b80d8

Add basic addressing mode support and one load.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24782 91177308-0d34-0410-b5e6-96231b3b80d8

eliminate some redundancy

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24781 91177308-0d34-0410-b5e6-96231b3b80d8

Use a combination of sethi and or to build arbitrary immediates.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24780 91177308-0d34-0410-b5e6-96231b3b80d8

Use sethi to build large immediates with zeros at the bottom

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24779 91177308-0d34-0410-b5e6-96231b3b80d8

Add shift and small immediate support

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24778 91177308-0d34-0410-b5e6-96231b3b80d8

Add some basic reg-reg instructions

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24777 91177308-0d34-0410-b5e6-96231b3b80d8

Add empty patterns to all F3_1 instructions

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24776 91177308-0d34-0410-b5e6-96231b3b80d8

Darwin API issue: indirect load of external and weak symbols.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24775 91177308-0d34-0410-b5e6-96231b3b80d8

Add some simple integer patterns.  This allows us to compile this:

int %test(int %A) {
  %B = add int %A, 1
  %C = xor int %B, 123
  ret int %C
}

into this:

test:
        save -96, %sp, %sp
        add %i0, 1, %l0
        xor %l0, 123, %i0
        restore %g0, %g0, %g0
        retl
        nop

for example.  I guess it would make sense to add reg/reg versions too.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24774 91177308-0d34-0410-b5e6-96231b3b80d8

Implement ret with operand, giving us this:

int %test(int %A) {
  ret int %A
}

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24773 91177308-0d34-0410-b5e6-96231b3b80d8

Add a pattern for 'ret'.  This now compiles:

void %test() { ret void }

:)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24772 91177308-0d34-0410-b5e6-96231b3b80d8

Add empty patterns for F3_2 instructions

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24771 91177308-0d34-0410-b5e6-96231b3b80d8

Implement LowerArguments, at least for the first 6 integer args

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24770 91177308-0d34-0410-b5e6-96231b3b80d8

Add the framework for a dag-dag isel

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24769 91177308-0d34-0410-b5e6-96231b3b80d8

Remove a few lines of dead code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24768 91177308-0d34-0410-b5e6-96231b3b80d8

asmprinter done, added crucial missing step

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24767 91177308-0d34-0410-b5e6-96231b3b80d8

Use the AsmPrinter for global variable init printing.  This eliminates a
bunch of code and causes V8 to start using the fancy .asciz directive that
the sun assembler supports.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24766 91177308-0d34-0410-b5e6-96231b3b80d8

Switch constant pool printing over to use the Shared AsmPrinter version

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24765 91177308-0d34-0410-b5e6-96231b3b80d8

Use the shared AsmPrinter code for some basic stuff.  No functionality
change except for fewer .section directives emitted

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24764 91177308-0d34-0410-b5e6-96231b3b80d8

Added an idea about any_extend for performance tuning.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24763 91177308-0d34-0410-b5e6-96231b3b80d8

Convert the remaining instructions over, branches and calls.  Fix a couple
minor bugs

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24762 91177308-0d34-0410-b5e6-96231b3b80d8

convert FP instructions to use an asmstring and operand list, allowing FP
programs to work on V8 again

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24761 91177308-0d34-0410-b5e6-96231b3b80d8

Added truncate.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24760 91177308-0d34-0410-b5e6-96231b3b80d8

Added anyext, modelled as zext on X86.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24759 91177308-0d34-0410-b5e6-96231b3b80d8

Yet another variant of getTargetNode().

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24758 91177308-0d34-0410-b5e6-96231b3b80d8

Added some isel ideas.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24757 91177308-0d34-0410-b5e6-96231b3b80d8

Added support for cmp, test, and conditional move instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24756 91177308-0d34-0410-b5e6-96231b3b80d8

Only lower SELECT when using DAG based isel.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24755 91177308-0d34-0410-b5e6-96231b3b80d8

X86 lowers SELECT to a cmp / test followed by a conditional move.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24754 91177308-0d34-0410-b5e6-96231b3b80d8

Support for read / write from explicit registers with FlagVT type.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24753 91177308-0d34-0410-b5e6-96231b3b80d8

Remove hidden DOS characters.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24752 91177308-0d34-0410-b5e6-96231b3b80d8

Fix VC++ level 4 warnings.  Because a base class has declared these private, VC++ complains it cannot automatically generate this methods.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24751 91177308-0d34-0410-b5e6-96231b3b80d8

Fix VC++ level 4 warnings.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24750 91177308-0d34-0410-b5e6-96231b3b80d8

Turn on string pooling for smaller binaries.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24749 91177308-0d34-0410-b5e6-96231b3b80d8

Added source file/line correspondence for dwarf (PowerPC only at this point.)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24748 91177308-0d34-0410-b5e6-96231b3b80d8

Weak and linkonce global vars should still have a .globl emitted for them

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24747 91177308-0d34-0410-b5e6-96231b3b80d8

Add a second vector type to the VRRC register class, and fix some patterns
so that tablegen can infer all types.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24746 91177308-0d34-0410-b5e6-96231b3b80d8

add some notes

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24745 91177308-0d34-0410-b5e6-96231b3b80d8

Add a couple more instrs

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24744 91177308-0d34-0410-b5e6-96231b3b80d8

remove some dead code

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24743 91177308-0d34-0410-b5e6-96231b3b80d8

asmprint pseudo instrs

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24742 91177308-0d34-0410-b5e6-96231b3b80d8

Autogenerate asmprinter for F3_2 instructions

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24741 91177308-0d34-0410-b5e6-96231b3b80d8

Switch F3_1 instructions over to use AsmStrings

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24740 91177308-0d34-0410-b5e6-96231b3b80d8

Plug in basic hooks for an autogenerated asm printer to fill in.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24739 91177308-0d34-0410-b5e6-96231b3b80d8

Add operand info for F3_[12] instructions, getting V8 back to basic functionality.
With this, Regression/CodeGen/SparcV8/basictest.ll now passes.  Lets hear it
for regression tests :)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24738 91177308-0d34-0410-b5e6-96231b3b80d8

A truly trivial testcase to ensure sparcv8 doesn't get completely broken
again.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24737 91177308-0d34-0410-b5e6-96231b3b80d8

Remove JIT support, which doesn't work.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24736 91177308-0d34-0410-b5e6-96231b3b80d8