MALI: utgard: upgrade DDK to r7p0-00rel1

Change-Id: If789dea2b6a9c11dc82c6f91d4bdd10761e2f7d1
Signed-off-by: chenzhen <chenzhen@rock-chips.com>

phy: rockchip-inno-usb2: disable id irq in pm suspend

The otg id voltage is provided from usb2 phy power. On some
rockchip platforms (e.g. rk3399), the usb2 phy power will be
turned off when enter pm suspend, this will trigger id fall
interrupt. But current code enable the ID interrupt consistently,
it may result in the mistake of ID changing operation even if
the state of ID pin is not changed. So disable ID irq when
suspend and enable when resume.

Change-Id: Icac35f13861fd639e4b422b31182a68add73836d
Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com>

drm/rockchip: hdmi: Add support for rk3228

RK3228 uses the Synopsys DWC HDMI TX controller and the INNO HDMI PHY to
enabling the integration of a complete HDMI Transmmiter interface.

Change-Id: I90f997968fb2de4165a31216c8aee8213089eab5
Signed-off-by: WeiYong Bi <bivvy.bi@rock-chips.com>

arm: rockchip_defconfig: enable CONFIG_PHY_ROCKCHIP_INNO_HDMI_PHY

Change-Id: If93eea5cfdf28042b75da0710287ad6c768338d2
Signed-off-by: WeiYong Bi <bivvy.bi@rock-chips.com>

phy: rockchip-inno-hdmi-phy: Add Inno HDMI PHY support

INNO HDMI 2.0 TX PHY is compliant with HDMI 2.0 specification
and optimized up to 3.72Gbps per TMDS link High-Definition
applications with supporting 3D Display and up to 4Kx2K@60/50Hz
UHD resolution at 10-bit YCbCr 4:2:0 video input mode.

Change-Id: I1f8b2e5c656378188dca8e02df6d52bad2919da8
Signed-off-by: WeiYong Bi <bivvy.bi@rock-chips.com>

drm: bridge: dw-hdmi: fix panic when misc_deregister()

Change-Id: I6ab7eb4e8a756e5ae62b181e36b9bff4f6dc7ebf
Signed-off-by: xuhuicong <xhc@rock-chips.com>

drm/rockchip: hdmi: Use Synopsys HDMI TX Controller YUV420 bus format

Change-Id: Ib787054dc1b6d81090a6aa94c3dabce91219e335
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>

drm/rockchip: vop: support Synopsys HDMI TX Controller YUV420 bus_format

MEDIA_BUS_FMT_UYYVYY8_0_5X24 and MEDIA_BUS_FMT_UYYVYY10_0_5X30 are
bus_format of YUV420 data between Rockchip vop and Synopsys HDMI
TX Controller.

Change-Id: Id06e7cc7703e9b12e1a7f64cdbacc5e8a98b2b45
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>

drm: bridge: dw-hdmi: add more check for HDCP function

On RK3328, dw-hdmi HDCP driver is loaded slower than dw-hdmi.
hdmi->hdcp->hdcp_start is NULL when dw-hdmi call the hdcp_start,
cause following system crash:

Unable to handle kernel NULL pointer dereference at virtual address 00000000
pgd = ffffff8009292000
[00000000] *pgd=000000007e1fe003, *pud=000000007e1fe003, *pmd=0000000000000000
Internal error: Oops: 86000005 [#1] SMP
Modules linked in:
CPU: 0 PID: 1 Comm: swapper/0 Not tainted 4.4.70 #418
Hardware name: Rockchip RK3328 EVB (DT)
task: ffffffc0003a0000 ti: ffffffc0003a8000 task.ti: ffffffc0003a8000
PC is at 0x0
LR is at dw_hdmi_update_power+0xef4/0x1004
pc : [<0000000000000000>] lr : [<ffffff800849e778>] pstate: 60000045
sp : ffffffc0003ab3b0
x29: ffffffc0003ab3b0 x28: 000000000000410b
x27: 0000000000000000 x26: 0000000000000000
x25: ffffffc07770d028 x24: 000000000000410b
x23: 0000000000000000 x22: 0000000000000001
x21: 0000000000000002 x20: ffffff8008c02000
x19: ffffff8008c02d90 x18: 0000000062475a46
x17: 0000000000000000 x16: 000000000000000e
x15: 0000000000000007 x14: 0ffffffffffffffd
x13: 0000000000000018 x12: 0101010101010101
x11: 7f7f7f7f7f7fff7f x10: fefefefeff01f305
x9 : ff7fff7f7f7f7f7f x8 : ffffff80091db5df
x7 : 0000000000000000 x6 : 0000000000000004
x5 : 0000000000000015 x4 : 0000000000140b82
x3 : 000000000106b1af x2 : 0000000000000001
x1 : 0000000000000000 x0 : ffffffc076e25e00

Change-Id: I0fccf9d8e06f7acdb56d8e5360acf0df026fee10
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>

UPSTREAM: drm: bridge: dw-hdmi: fix input format/encoding from plat_data

The plat_data->input_bus_format and plat_data->input_bus_encoding
are unsigned long and are always >=0, but the value 0 was still
considered as RGB888 for input_bus_format and default color space
for input_bus_encoding in the reworked code.

This patch changes the if statement check for a non-zero value to
either use the default input bus_format and/or bus_encoding for a zero
value and the provided bus_format and/or bus_encoding for a
non zero value.

Thanks to Dan Carpenter for his bug report at [1].

Tested on Amlogic P230 (with CSC enabled for YUV444 to RGB) and Rockchip
RK3288 ACT8846 EVB Board (no CSC involved, direct RGB passthrough).

[1] http://lkml.kernel.org/r/20170406052120.GA26578@mwanda

Cc: Dan Carpenter <dan.carpenter@oracle.com>
Fixes: def23aa7e982 ("drm: bridge: dw-hdmi: Switch to V4L bus format and encodings")
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Archit Taneja <architt@codeaurora.org>
[narmstrong@baylibre.com: reworded commit message and added Fixes tag]
Link: http://patchwork.freedesktop.org/patch/msgid/1491471244-24989-1-git-send-email-narmstrong@baylibre.com
Change-Id: I1b6c08e3fe468c01fcd721fe4b4d6ec95c73528b
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
(cherry picked from commit e20c29aa722a90f3b8092b340362eabe488dbfc4)

UPSTREAM: drm: bridge: dw-hdmi: Switch to V4L bus format and encodings

Switch code to use the newly introduced V4L bus formats IDs instead of custom
defines. Also use the V4L encoding defines.

Some display pipelines can only provide non-RBG input pixels to the HDMI TX
Controller, this patch takes the pixel format from the plat_data if provided.

Change-Id: I2b70ed0f3cab8c6873bb407977738677375b24b0
Reviewed-by: Jose Abreu <joabreu@synopsys.com>
Reviewed-by: Archit Taneja <architt@codeaurora.org>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
(cherry picked from commit def23aa7e9821a3dfe3fb7b139dd0229a89fdeb0)

UPSTREAM: media: uapi: Add RGB and YUV bus formats for Synopsys HDMI TX Controller

In order to describe the RGB and YUV bus formats used to feed the
Synopsys DesignWare HDMI TX Controller, add missing formats to the
list of Bus Formats.

Documentation for these formats is added in a separate patch.

Change-Id: Ic2cab2bbe6caed5e5b6e86c60a58f26046d259be
Reviewed-by: Archit Taneja <architt@codeaurora.org>
Reviewed-by: Jose Abreu <joabreu@synopsys.com>
Acked-by: Hans Verkuil <hans.verkuil@cisco.com>
Acked-by: Mauro Carvalho Chehab <mchehab@s-opensource.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Sean Paul <seanpaul@chromium.org>
Link: http://patchwork.freedesktop.org/patch/msgid/1491230558-10804-3-git-send-email-narmstrong@baylibre.com
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
(cherry picked from commit d0353118fd589c127875290017c7fdd266937bee)

drm/rockchip: vop: initital crtc pll status

If the crtc pll status is not init, always cause mode_changed
at first dclk source generate, that would cause logo flush
fixup(10a90aa drm/rockchip: support setting specail pll for hdmi)

Change-Id: I0ee20fd098654ff89f268be82b50d2d5b605e9d5
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>

drivers: rk_nand: update ftl to support slc nand and micron L04A

1. support 128MB and 256MB slc nand flash
2. support micron L04A 3D mlc nand flash
3. fix 3036 read sn fail issue

Change-Id: If08b3f8bd37c9d9c161b733f6127b137a8bfdd4f
Signed-off-by: Zhaoyifeng <zyf@rock-chips.com>

soc: rockchip: Add dummy rockchip_pm_register_notify_to_dmc

build fix for CONFIG_ROCKCHIP_PM_DOMAINS=n

Change-Id: Iffa0bfa3ab7fc78360341f188f645d2579edde2e
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>

camera: rockchip: camsys driver v0.0x22.1

gpio0_D is unavailable on rk3288 with current pinctrl driver.

Change-Id: I7d38ebd3b00ac0df31861406f758bdd9e57f9903
Signed-off-by: xcq <shawn.xu@rock-chips.com>

Revert "pinctrl: rockchip: Add rk3288 GPIO0_D0 ~ GPIO0_D7 pins support"

This reverts commit 1d9964a98931ac8f8680664e2a0731ecffc3448b.

Double confirmation, GPIO0_D0 ~ GPIO0_D7 pins are not connected to pad,
this is a wrong commit, revert this commit.

Change-Id: Iebec11ee47a68fe51ec90361fd412d05df832998
Signed-off-by: David Wu <david.wu@rock-chips.com>

power_supply: add cw2015 battery support

Change-Id: I36d65b9765a3303169f0ff60025d9ae722ceb1a9
Signed-off-by: Shunqing Chen <csq@rock-chips.com>

drm: bridge: dw-hdmi: add hdcp1.4 support

First, write hdcp key by "ProvisioningTool" if you want to
enable hdcp function, or else will auth fail.

To check whether the hdcp is enable or not
  #cat /sys/class/misc/hdmi_hdcp1x/enable
  0:hdcp is disabled
  1:hdcp is enabled, hdmi screen will be pink if it is failed;
  2:hdcp is enabled, hdmi screen will be normal if it is failed;

Enable or disable hdcp function
  #echo 0 > /sys/class/misc/hdmi_hdcp1x/enable
  #echo 1 > /sys/class/misc/hdmi_hdcp1x/enable
  #echo 2 > /sys/class/misc/hdmi_hdcp1x/enable

Get the status of hdcp
  #cat /sys/class/misc/hdmi_hdcp1x/status
  The result will be one of the follow list:
    hdcp disable;
    hdcp_auth_start
    hdcp_auth_success;
    hdcp_auth_fail;
    unknown status.

Change-Id: Iac6c7d6a1196ce9cf2869d7916bbe6c8941ec13b
Signed-off-by: xuhuicong <xhc@rock-chips.com>

clk: rockchip: rk3228: add SCLK_SDIO_SRC clk id

This patch exports sdio src clock for dts reference.

Change-Id: I3e83cce4da3d82af4b18df43ecd51c504d308c02
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

drm/rockchip: gem: don't limit to 32bit mapping when not support LPAE

Change-Id: I3d2b41cfb0be3122ccb291802feb950017acdf44
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>

drm/rockchip: hdmi: correct 3328 hdmi phy power up timing

According to spec, TMDS driver should power up between PLL
power up and PLL lock.

There is an mistake of pdata en register, the real register
is reg2 bit0, not reg1 bit0.

Change-Id: I9d2b707cbcfd70b63f4a1a277a85f21b62643d2e
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>

drm/rockchip: logo: restore display if show logo failed

Change-Id: I554eaff439b6cd13770fb81ec5c9df6693e17f29
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>

dmaengine: pl330: _loop_cyclic supports unaligned size

Change-Id: If724fb0c414edc13bba94def8da78c28a4cec69a
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>

drm/rockchip: vop: correct clk_set_parent return value check

Change-Id: I3da501169739759426c83a3b7e6e255c717e226c
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>

drm/rockchip: vop: get rid of max_output.height check

Actually vop hardware has no output height limit, so no
need limit display with max_output.height

Change-Id: Ide70cb28af9a23c1a12c068168b13aac37041b28
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>

ARM64: dts: rk3328-evb: set hdmi ddc clock rate to 50KHz

Change-Id: I59bc54a17d697e742a3753baba692f3541f742e4
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>

driver: mpu: to support mpu6881/mpu6880

Change-Id: I731788cd35d27d2aab946ccb22f744aad85f7be3
Signed-off-by: Zorro Liu <lyx@rock-chips.com>

ARM64: dts: rk3368-p9: set sleep mode config RKPM_SLP_ARMOFF

Change-Id: I65b87a37f029e316cf048bf7da790d51a046cca2
Signed-off-by: Zorro Liu <lyx@rock-chips.com>

ARM64: dts: rockchip: enable rockchip_suspend node of rk3368-p9 and rk3368-sheep board

Change-Id: Iff11ec889c372f279cf638ff2f3f2b72824abd4c
Signed-off-by: Zorro Liu <lyx@rock-chips.com>

arm64: dts: rockchip: enable dp for rk3399 evb rev3 board

Change-Id: I91043fd5caa8a639844658cc0410372785b1c43d
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>

arm64: dts: rockchip: rk3399: add dclk pll sources

Change-Id: I0e29d67d5e3738b18a7407a049d216f8dcebb8e8
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>

Documentation: dt-bindings: rockchip: introduce dclk_source

Change-Id: Iee4d40ede334f418fd4edb51319b5e03f25467c0
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>

Documentation: dt-bindings: rockchip: introduce display plls

Change-Id: Ifa7129bc5dd625c7f78040b0d506930be24c5aa0
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>

drm/rockchip: support setting specail pll for hdmi

In order to get lower jitter clock for hdmi tmds, Hardware
design that: direct get tmds clock from vpll, bypass vop.

This design can make hdmi good works, but also limit hdmi's
clock source, the vop which hdmi use need also assign to vpll,
and use same clock rate, it's hardware limitation.

This patch add a mechanism to select dclk's parent pll, then
can allocate correct pll for hdmi.

Change-Id: I9e3b4b6d3756c409782df0605706be4203d69a32
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
Suggested-by: Heiko Stuebner <heiko@sntech.de>

driver: sensor: ak09911: to match hal code, compatible with ak8963

Change-Id: Ia5768a4466512063948c48c2139356522a4557ac
Signed-off-by: Zorro Liu <lyx@rock-chips.com>

dmaengine: pl330: redefine the cyclic transfer

dmaengine_prep_dma_cyclic, to use buf_addr with size buf_len,
generate an interrupt every period_len. But DMA must restart
every period_len, it may be blocked. If i2s use it, it may
cause sound break. Infiniteloop is helpful to solve this
issue. In infiniteloop mode, when DMA transfers all buf_len
data, it goes back to the start of buf_addr and continue to
transfer endless.

Change-Id: Ibbc92c416d0a9dd58633e7991176c86300c3da98
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>

arm64: dts: rockchip: config dr_mode as otg for usb on rk3328-evb

Because we have supported to force otg mode for rk3328 in the commit
2b9b897141f1 ("phy: rockchip-inno-usb2: support to force otg mode"),
so let's config dr_mode as otg for usb otg port, and then user can
use otg peripheral mode and host mode as needed.

Change-Id: I6f55fb2aad1b8c49498af829475a8b59215251e5
Signed-off-by: William Wu <william.wu@rock-chips.com>

arm: dts: rk322x-android: add otg vbus gpio for usb2 phy0

This patch adds otg vbus gpio for usb2 phy0, and then we
can control otg vbus for otg host mode.

Change-Id: I685060270f9cb0963931a84035cad7286d99a469
Signed-off-by: William Wu <william.wu@rock-chips.com>

phy: rockchip-inno-usb2: support to force otg mode

This patch creates an usb2 phy attribute group and
provides an attribute "otg_mode" for otg port to
force otg mode independently of the voltage of otg
id pin.

In order to implement the force mode function, we can
select otg plug indicator output (AKA iddig) from GRF,
and set GRF USB otg plug indicator to "0" or "1" to
control iddig status.

We only support rk322x/rk3328 to force otg mode for
the time being.

And we need to disable usb auto suspend function if
we want to force otg mode. Add 'usbcore.autosuspend=-1'
in cmdline to disable usb auto suspend.

Usage:
[1] Force host mode
    echo host > /sys/devices/platform/<u2phy dev name>/mode

[2] Force peripheral mode
    echo peripheral > /sys/devices/platform/<u2phy dev name>/mode

[3] Force otg mode
    echo otg > /sys/devices/platform/<u2phy dev name>/mode

Legacy Usage:
[1] Force host mode
    echo 1 > /sys/devices/platform/<u2phy dev name>/mode

[2] Force peripheral mode
    echo 2 > /sys/devices/platform/<u2phy dev name>/mode

[3] Force otg mode
    echo 0 > /sys/devices/platform/<u2phy dev name>/mode

Change-Id: I875b60b0390e3bd9af34b740cba8f5d53e1df752
Signed-off-by: William Wu <william.wu@rock-chips.com>

dt-bindings: display: screen-timing: add physical size for h546dlb01

Change-Id: I51ba6c2bdacddbc16dbf79df1f36ef6f09340989
Signed-off-by: WeiYong Bi <bivvy.bi@rock-chips.com>

phy: rockchip-inno-usb2: fix possibe deadlock

The commit 611ec35fa148 ("phy: rockchip-inno-usb2: fix some
race conditions") use mutex lock to protect charger detect
work, but it will cause the following possible deadlock.

[ INFO: possible circular locking dependency detected ]
4.4.66 #563 Not tainted
-------------------------------------------------------
kworker/3:1/145 is trying to acquire lock:
(&rport->mutex){+.+...}, at: [<ffffff80083f286c>] rockchip_chg_detect_work+0x6c/0x3d0

but task is already holding lock:
((&(&rport->chg_work)->work)){+.+...}, at: [<ffffff80080be6e4>] process_one_work+0x1c4/0x6ac

which lock already depends on the new lock.
the existing dependency chain (in reverse order) is:

-> #1 ((&(&rport->chg_work)->work)){+.+...}:
[<ffffff80080fda40>] __lock_acquire+0x15c0/0x195c
[<ffffff80080fe5e8>] lock_acquire+0x190/0x250
[<ffffff80080bf534>] flush_work+0x4c/0x274
[<ffffff80080bf944>] __cancel_work_timer+0x130/0x1c0
[<ffffff80080bf9fc>] cancel_delayed_work_sync+0x10/0x18
[<ffffff80083f17a8>] rockchip_usb2phy_exit+0x54/0x6c
[<ffffff80083f07ac>] phy_exit+0x64/0xb4
[<ffffff8008772810>] dwc3_core_exit+0x44/0x98
[<ffffff80087728b0>] dwc3_suspend_common+0x4c/0x5c
[<ffffff8008772a68>] dwc3_runtime_suspend+0x38/0x5c
[<ffffff8008571784>] pm_generic_runtime_suspend+0x28/0x38
[<ffffff8008573464>] __rpm_callback+0x40/0x74
[<ffffff80085734f4>] rpm_callback+0x5c/0x80
[<ffffff8008573bc4>] rpm_suspend+0x31c/0x688
[<ffffff80085751ec>] __pm_runtime_suspend+0x58/0xa4
[<ffffff800877efc0>] dwc3_rockchip_probe+0x3f8/0x574
[<ffffff800856bcd0>] platform_drv_probe+0x58/0xa4
[<ffffff8008569bb0>] driver_probe_device+0x118/0x2b0
[<ffffff8008569e9c>] __device_attach_driver+0x88/0x98
[<ffffff8008567f4c>] bus_for_each_drv+0x7c/0xac
[<ffffff80085699e4>] __device_attach+0xa8/0x128
[<ffffff800856a00c>] device_initial_probe+0x10/0x18
[<ffffff8008569000>] bus_probe_device+0x2c/0x90
[<ffffff800856948c>] deferred_probe_work_func+0x78/0xa8
[<ffffff80080be858>] process_one_work+0x338/0x6ac
[<ffffff80080bfd54>] worker_thread+0x300/0x428
[<ffffff80080c5758>] kthread+0x104/0x10c
[<ffffff8008083080>] ret_from_fork+0x10/0x50

-> #0 (&rport->mutex){+.+...}:
[<ffffff80080faacc>] print_circular_bug+0x64/0x2c4
[<ffffff80080fd70c>] __lock_acquire+0x128c/0x195c
[<ffffff80080fe5e8>] lock_acquire+0x190/0x250
[<ffffff8008c67ac0>] mutex_lock_nested+0x80/0x3d0
[<ffffff80083f286c>] rockchip_chg_detect_work+0x6c/0x3d0
[<ffffff80080be858>] process_one_work+0x338/0x6ac
[<ffffff80080bfd54>] worker_thread+0x300/0x428
[<ffffff80080c5758>] kthread+0x104/0x10c
[<ffffff8008083080>] ret_from_fork+0x10/0x50

other info that might help us debug this:

Possible unsafe locking scenario:

        CPU0                    CPU1
        ----                    ----
   lock((&(&rport->chg_work)->work));
                                lock(&rport->mutex);
                                lock((&(&rport->chg_work)->work));
   lock(&rport->mutex);

  *** DEADLOCK ***

2 locks held by kworker/3:1/145:

stack backtrace:
CPU: 3 PID: 145 Comm: kworker/3:1 Not tainted 4.4.66 #563
Hardware name: Rockchip RK3399 Evaluation Board v3 (Android) (DT)
Workqueue: events rockchip_chg_detect_work
Call trace:
[<ffffff800808a814>] dump_backtrace+0x0/0x1c8
[<ffffff800808a9f0>] show_stack+0x14/0x1c
[<ffffff80083c1fa0>] dump_stack+0xb0/0xec
[<ffffff80080fad10>] print_circular_bug+0x2a8/0x2c4
[<ffffff80080fd70c>] __lock_acquire+0x128c/0x195c
[<ffffff80080fe5e8>] lock_acquire+0x190/0x250
[<ffffff8008c67ac0>] mutex_lock_nested+0x80/0x3d0
[<ffffff80083f286c>] rockchip_chg_detect_work+0x6c/0x3d0
[<ffffff80080be858>] process_one_work+0x338/0x6ac
[<ffffff80080bfd54>] worker_thread+0x300/0x428
[<ffffff80080c5758>] kthread+0x104/0x10c
[<ffffff8008083080>] ret_from_fork+0x10/0x50

Change-Id: I4289afb05d334bf79000090f9071cf428817a583
Signed-off-by: William Wu <william.wu@rock-chips.com>

arm64: rockchip_linux_defconfig: enable MPP_SERVICE

Change-Id: I12cb15a44e31f768bac960e3a5e6b9371d221ed3
Signed-off-by: Hans Yang <yhx@rock-chips.com>

drm/rockchip: limit gem buffer to 32bit mapping

Change-Id: I64537668aa10a2e26bdd19ac79bc417aa6c4a437
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>

drm: support loader protect for panel

Change-Id: Ie9330e3380a4925a4b7603e7206f1e0d186d2156
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>

ARM64: dts: rk3328-evb: enable vepu & h265e default

Change-Id: I94685dbeea3ceffa106593ff597f50404f58f34a
Signed-off-by: Jung Zhao <jung.zhao@rock-chips.com>

ARM64: dts: rk3328: add vepu & h265e dts node

Change-Id: I2990ac7e43d4b2d2efbf5e9cf3abe124e8767648
Signed-off-by: Jung Zhao <jung.zhao@rock-chips.com>

driver: video: rockchip: add new driver of vpu

this driver only support h264e & h265e. if you want to
enable the driver, you must modify the menuconfig and
turn on MPP_SERVICE & MPP_DEVICE.

Change-Id: I7f1c6e473eaf7aedb4fa86791412b5fbcb2c531d
Signed-off-by: buluess.li <buluess.li@rock-chips.com>
Signed-off-by: Jung Zhao <jung.zhao@rock-chips.com>

Merge tag 'lsk-v4.4-17.05-android' of git://git.linaro.org/kernel/linux-linaro-stable.git

LSK 17.05 v4.4-android

* tag 'lsk-v4.4-17.05-android': (266 commits)
  BACKPORT: mm/slab: clean up DEBUG_PAGEALLOC processing code
  Linux 4.4.70
  UPSTREAM: arm64: hibernate: Support DEBUG_PAGEALLOC
  BACKPORT: arm64: vmlinux.ld: Add mmuoff data sections and move mmuoff text into idmap
  BACKPORT: arm64: Create sections.h
  ANDROID: uid_sys_stats: defer io stats calulation for dead tasks
  ANDROID: AVB: Fix linter errors.
  ANDROID: AVB: Fix invalidate_vbmeta_submit().
  drivers: char: mem: Check for address space wraparound with mmap()
  nfsd: encoders mustn't use unitialized values in error cases
  drm/edid: Add 10 bpc quirk for LGD 764 panel in HP zBook 17 G2
  PCI: Freeze PME scan before suspending devices
  PCI: Fix pci_mmap_fits() for HAVE_PCI_RESOURCE_TO_USER platforms
  tracing/kprobes: Enforce kprobes teardown after testing
  osf_wait4(): fix infoleak
  genirq: Fix chained interrupt data ordering
  uwb: fix device quirk on big-endian hosts
  metag/uaccess: Check access_ok in strncpy_from_user
  metag/uaccess: Fix access_ok()
  iommu/vt-d: Flush the IOTLB to get rid of the initial kdump mappings
  ...

Revert "UPSTREAM: pinctrl: rockchip: avoid hardirq-unsafe functions in irq_chip"

This reverts commit a8b4e18cf1e98ed3b36175cb4e3ef422c03ac01c.

Which will cause such error:

BUG: sleeping function called from invalid context at kernel/locking/mutex.c:620
in_atomic(): 1, irqs_disabled(): 128, pid: 141, name: irq/95-fusb302
1 lock held by irq/95-fusb302/141:
 #0:  (&(&chip->irq_lock)->rlock){......}, at: [<ffffff800859e3a0>] fusb_irq_disable+0x20/0x68
irq event stamp: 52
hardirqs last  enabled at (51): [<ffffff80080bcc30>] queue_work_on+0x68/0x80
hardirqs last disabled at (52): [<ffffff8008c6f41c>] _raw_spin_lock_irqsave+0x20/0x60
softirqs last  enabled at (0): [<ffffff800809e9ec>] copy_process.isra.54+0x390/0x1728
softirqs last disabled at (0): [<          (null)>]           (null)
Preemption disabled at:[<ffffff800859e3a0>] fusb_irq_disable+0x20/0x68

CPU: 5 PID: 141 Comm: irq/95-fusb302 Not tainted 4.4.70 #30
Hardware name: Rockchip RK3399 Evaluation Board v3 (Android) (DT)
Call trace:
[<ffffff800808a82c>] dump_backtrace+0x0/0x1c4
[<ffffff800808aa04>] show_stack+0x14/0x1c
[<ffffff80083c3b90>] dump_stack+0xa8/0xe0
[<ffffff80080cf560>] ___might_sleep+0x214/0x224
[<ffffff80080cf5e4>] __might_sleep+0x74/0x84
[<ffffff8008c6c1ac>] mutex_lock_nested+0x48/0x3cc
[<ffffff80083fe2b0>] rockchip_irq_bus_lock+0x28/0x34
[<ffffff800810b680>] __irq_get_desc_lock+0x68/0x88
[<ffffff800810d558>] __disable_irq_nosync+0x28/0x70
[<ffffff800810d5ac>] disable_irq_nosync+0xc/0x14
[<ffffff800859e3b4>] fusb_irq_disable+0x34/0x68
[<ffffff800859e410>] cc_interrupt_handler+0x28/0x38
[<ffffff800810cd48>] irq_thread_fn+0x28/0x68
[<ffffff800810cf80>] irq_thread+0x130/0x234
[<ffffff80080c58e8>] kthread+0x104/0x10c
[<ffffff8008083080>] ret_from_fork+0x10/0x50

or

BUG: sleeping function called from invalid context at kernel/locking/mutex.c:620
in_atomic(): 1, irqs_disabled(): 128, pid: 0, name: swapper/0
INFO: lockdep is turned off.
irq event stamp: 111558
hardirqs last  enabled at (111557): [<ffffff8008116cdc>] rcu_idle_exit+0x70/0x80
hardirqs last disabled at (111558): [<ffffff80080f1078>] cpu_startup_entry+0xc0/0x42c
softirqs last  enabled at (111554): [<ffffff80080a6794>] _local_bh_enable+0x3c/0x44
softirqs last disabled at (111553): [<ffffff80080a7000>] irq_enter+0x28/0x64
Preemption disabled at:[<ffffff80080f1308>] cpu_startup_entry+0x350/0x42c

CPU: 0 PID: 0 Comm: swapper/0 Not tainted 4.4.70 #30
Hardware name: Rockchip RK3399 Evaluation Board v3 (Android) (DT)
Call trace:
[<ffffff800808a82c>] dump_backtrace+0x0/0x1c4
[<ffffff800808aa04>] show_stack+0x14/0x1c
[<ffffff80083c3b90>] dump_stack+0xa8/0xe0
[<ffffff80080cf560>] ___might_sleep+0x214/0x224
[<ffffff80080cf5e4>] __might_sleep+0x74/0x84
[<ffffff8008c6c1ac>] mutex_lock_nested+0x48/0x3cc
[<ffffff80083fe2b0>] rockchip_irq_bus_lock+0x28/0x34
[<ffffff800810b680>] __irq_get_desc_lock+0x68/0x88
[<ffffff800810d558>] __disable_irq_nosync+0x28/0x70
[<ffffff800810d5ac>] disable_irq_nosync+0xc/0x14
[<ffffff8008621f20>] bcmsdh_oob_intr_set+0x4c/0x6c
[<ffffff8008621f5c>] wlan_oob_irq+0x1c/0x38
[<ffffff800810bd28>] handle_irq_event_percpu+0x150/0x3e8
[<ffffff800810c004>] handle_irq_event+0x44/0x74
[<ffffff800810f53c>] handle_level_irq+0xe4/0x11c
[<ffffff800810b228>] generic_handle_irq+0x1c/0x2c
[<ffffff80083fe068>] rockchip_irq_demux+0xe0/0x188
[<ffffff800810b228>] generic_handle_irq+0x1c/0x2c
[<ffffff800810b5b0>] __handle_domain_irq+0xb0/0xec
[<ffffff8008080f70>] gic_handle_irq+0xbc/0x154

Change-Id: I7cfbeaf7df17fc4e923e89917199b7f1c773455a
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>

arm64: dts: rk3328: dmac: add peripherals-req-type-burst

Change-Id: I097e13f3e9e88c5624bcd67eaaf66d773465939b
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>

ARM: dts: rk3xxx: dmac: add peripherals-req-type-burst

Change-Id: Iab3df00b2d228498d059ef2ede8d2ed0e598f408
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>

ARM: dts: rk322x: dmac: add peripherals-req-type-burst

Change-Id: I2a748a2a7a5b00a2c7ff116bac7358d6267cb45f
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>

ARM: dts: rk312x: dmac: add quirks

1. arm,pl330-broken-no-flushp
2. peripherals-req-type-burst

Change-Id: I33a357e10a011b5c22fb8aa7c8362fa20f051d66
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>

ASoC: rockchip: i2s: fixup clk div

we found mclk maybe not precise as required because of PLL,
but it still can be used and no side effect. for example, if we
require mclk 11289600, but get 11289598, it doesn't matter.
so using DIV_ROUND_CLOSEST to fix it.

Change-Id: If8453a7a08b319da81b07d572b02247bd7e7bd27
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>

arm64: dts: rockchip: enable video decoder for RK3328 EVB

This commit would enable the VDPU and RKVDEC devices.
The VDPU works in the non combo mode.

Change-Id: I643350d5a2ac17759984fda2e95fb2b82701e7cf
Signed-off-by: Randy Li <randy.li@rock-chips.com>

video: rockchip: vpu: introduce safe reset method

Even the same type video IP would request a different numbers
of reset control.

From the RK3328 times, the video IP also request decrease the
frequency of the clock to lower than 300 MHZ before resetting.
It seems no hard to apply it into the previous platform.

Change-Id: Iacf1accf24c8776bb8b425b613e6e34215380203
Signed-off-by: Randy Li <randy.li@rock-chips.com>

arm64: dts: rockchip: add video decoder nodes on rk3328

Jung and I meet some problem the video decoder, so
we just release the VDPU standalone this time.

It seems that the iommu can't attach to two different
IP at the same time.

Change-Id: I24d73cd5ab2c3d32da6ef29661061c7fda9186f2
Signed-off-by: Randy Li <randy.li@rock-chips.com>

ARM: dts: rockchip: enable sdmmc and sdio for rk322x-android

Change-Id: Ibed59e1bded5e81dd2f84438d3fa16a3dc0a1ba1
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>

ARM: dts: rockchip: add sdmmc and sdio nodes for rk3228 SoC

Change-Id: I50309e972b9c606782195b91d1f034f1336af0cd
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>

ARM: dts: rockchip: fix compatible string for eMMC node of rk3228 SoC

Change-Id: I2ee59491c79dd0e8a201f6478c6ca40cb8437e42
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>

Documentation: rockchip-dw-mshc: add description for rk3228

Add "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc" for
dwmmc on rk322x platform.

Change-Id: I8217d237260a33ce5b115080cf4d41ad4a5733e8
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>

arm64: dts: rk3399: sapphire: enabled dp default

Change-Id: Icfdea500e35164c90c75c9b538285a2a9691cbb6
Signed-off-by: Wu Liangqing <wlq@rock-chips.com>

clk: rockchip: rk3228: add more flags for dclk_vop

Change-Id: Ie5838b20f419d667831e7d99f4b95856731ef0ef
Signed-off-by: WeiYong Bi <bivvy.bi@rock-chips.com>

clk: rockchip: rk3228: export hdmiphy clock

Change-Id: Ib7acd4c2f576ad320e069ab2bd9137156062e2d9
Signed-off-by: WeiYong Bi <bivvy.bi@rock-chips.com>

arm64: dts: rk3328-evb: enable hdmi audio

Change-Id: Ic67744ac5554b90b6d9f85eeedf4721562f8155f
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>

phy: rockchip-inno-usb2: fix some race conditions

There are some race conditions related to phy power on/off
and otg charger detection work, otg sm work. I can find at
least three race conditions at present.

Race condition[1]:
The first race condition involving phy power on/off which
may be caused by the following case.

Test on rk3399 evaluation board Type-C0, connect to PC usb
port with Type-C cable, then phy power on/off operation may
be done twice because of race condition between phy driver
and usb controller driver.

CPU 0:
- rockchip_usb2phy_bvalid_irq()
 - rockchip_usb2phy_otg_sm_work()
  - detect connect to PC usb, do phy power on
   - rockchip_usb2phy_power_on()

CPU 1:
- dwc3 driver do runtime resume process
 - dwc3_runtime_resume()
  - dwc3_core_init()
   - phy_power_on()
    - rockchip_usb2phy_power_on()

Although we use a suspended flag in rockchip_usb2phy_power_on()
to avoid doing the same things twice, but it's not enough to
prevent race condition if phy driver and usb controller driver
access the rockchip_usb2phy_power_on() at the same time. This
race condition may cause clk management unbalanced.

Race condition[2]:
The second race condition related to phy power on/off and otg
charger detection work. We need to keep the usb phy staying in
suspend mode when do usb charger detection. But now it don't
have any protection to prevent the other threads to operate phy
during charger detection.

The problem can also be easily reproduced on rk3399 evaluation
board Type-C0 when connect to PC usb port with Type-C cable.

CPU 0:
- rockchip_chg_detect_work()
 - power off phy and start to do charge detection work

CPU 1:
- dwc3 driver do runtime resume process
 - dwc3_runtime_resume()
  - dwc3_core_init()
   - phy_power_on()
    - power on phy again

This race condition may cause charger detection and later usb
enumeration abnormally.

Race condition[3]:
The third race condition involving otg sm work. The otg sm
work can be interrupted by bvalid irq, and the bvalid irq
handler rockchip_usb2phy_bvalid_irq() will do otg sm work,
which may cause unknown error.

This patch uses mutex lock to protect the phy operations,
otg charger detection work and otg sm work.

Change-Id: Ic6845a10b3e69fe9ae6cf0b2d4e2beb098232abd
Signed-off-by: William Wu <william.wu@rock-chips.com>

Revert "drm/rockchip: vop: round_up pitches to word align"

This reverts commit 7e705c4974eaa8abaf44cb1542d3ec49d520fde8.

Change-Id: I498ade43de012f65ea39624bd2982b4a84bcbf54
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>

drm/rockchip: logo: round_up pitches to word align

Change-Id: I836193ca37fb62c72c61aa47a807959c3c189925
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>

drm/rockchip: logo: use unique plane property logo mirror

The logo framework use state->rotation may conflict to common drm
update, cause display abnormal

Change-Id: I09b6b898a7606cd05371af1f4b25254945923d0d
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>

UPSTREAM: clk: rockchip: mark some special clk as critical on rk3368

The jtag clk no driver to handle them.
But this clk need enable,so make it as critical.

The ddrphy/ddrupctl clks no driver to handle them,
Chip design requirements for these clock to always on,

The pmu_hclk_otg0 is Chip design defect, must be always on,

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from git.kernel.org mmind/linux-rockchip.git v4.13-clk/next
 commit 223c24be740d293519ef8e03f5c075fab5512fd2)

Conflicts:
drivers/clk/rockchip/clk-rk3368.c

Change-Id: I31c1c7efb7a83652501a7f53ff5931d9f308f736
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

UPSTREAM: clk: rockchip: mark noc and some special clk as critical on rk3288

The atclk/dbg/jtag/hsic-xin12m/pclk_core clks no driver to handle them.
But this clks need enable,so make it as ignore_unused for now.

The ddrupctl0/ddrupctl1/publ0/publ1 clks no driver to handle them,
Chip design requirements for these clock to always on,

The pmu_hclk_otg0 is Chip design defect, must be always on,

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from git.kernel.org mmind/linux-rockchip.git v4.13-clk/next
 commit 55bb6a633c33caf68ab470907ecf945289cb733d)

Conflicts:
drivers/clk/rockchip/clk-rk3288.c

Change-Id: I6271a903deb9ca21b5e74fd2c1ad4cf69f7021e1
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

UPSTREAM: clk: rockchip: mark pclk_ddrupctl as critical_clock on rk3036

No driver to handle this clk yet, but chip design requiress for this clock
supplying the ddr controller to be always on.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from git.kernel.org mmind/linux-rockchip.git v4.13-clk/next
 commit f2893aaba435fcb55b86dc1be8c6f64f8d60e64b)

Change-Id: I3cd9578f73a69eb0f09d1f40c22ee55b393149aa
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

UPSTREAM: clk: rockchip: Make uartpll a child of the gpll on rk3036

The shared uart-pll is on boot a child of the apll that can get changed
by cpu frequency scaling. So move it away to the more stable gpll to
make sure the uart doesn't break on cpu frequency changes.

This turned up during the 4.11 merge-window when commit
6a171b299379 ("serial: 8250_dw: Allow hardware flow control to be used")
added general termios enablement making the uart on rk3036 change
frequency and thus making it susceptible for the frequency scaling issue.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
(cherry picked from git.kernel.org mmind/linux-rockchip.git v4.13-clk/next
 commit f8ba2d68e54fbca340ad0fce97397291ba9637bc)

Change-Id: Ia8683d7b49523284043457727665d7e58d1551ec
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

UPSTREAM: clk: rockchip: add "," to mux_pll_src_apll_dpll_gpll_usb480m_p on rk3036

The mux_pll_src_apll_dpll_gpll_usb480m_p parent list was missing a ","
between the 3rd and 4th parent names, making them fall together and thus
lookups fail. Fix that.

Fixes: 5190c08b2989 ("clk: rockchip: add clock controller for rk3036")
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
(cherry picked from git.kernel.org mmind/linux-rockchip.git v4.13-clk/next
 commit 9b1b23f03abdd25ffde8bbfe5824b89bc0448c28)

Change-Id: I535b64fc7c902a4e9c64b4b803bb03126b7ba110
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

UPSTREAM: clk: rockchip: mark noc and some special clk as critical on rk3228

The jtag/bus/peri/initmem/rom/stimer/phy clks no driver to handle them.
But this clks need enable,so make it as critical.

The ddrupctl/ddrmon/ddrphy clks no driver to handle them,
Chip design requirements for these clock to always on,

The hclk_otg_pmu is Chip design defect, must be always on,
The new document will update the description of this clock.

All these non-noc/non-arbi clocks,IC suggest always on,
Because it's have some order limitation, between the NOC clock switch
and bus IDLE(or pd on/off).

The software is not very good to solve this constraint.
Always on these clocks, has no effect on the system power consumption.
The new document will update the description of these clock.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from git.kernel.org mmind/linux-rockchip.git v4.13-clk/next
 commit f18c0994cda54dc21d3b0ce2ba130b5ea8f58666)

Conflicts:
drivers/clk/rockchip/clk-rk3228.c

Change-Id: Ie2c4c8d2c73a62efe96e64a3ec638970e82051d1
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

arm: rockchip_defconfig: support dtb appended and bootargs extended

This patch support using appended device tree blob to zImage and
supplementing the appended DTB with traditional ATAG information.

Change-Id: I8e8e63513c17544fdafd9107fda425740c63220e
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>

rk: gcc-wrapper.py ignore atags_to_fdt.c:98

Change-Id: Ie7d1c5b7ba5d1147c1996d73f19d5e0d768998ec
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>

UPSTREAM: ARM: 8500/1: fix atags_to_fdt with stack-protector-strong

Building with CONFIG_CC_STACKPROTECTOR_STRONG triggers protection code
generation under CONFIG_ARM_ATAG_DTB_COMPAT but this is too early for
being able to use any of the stack_chk code. Explicitly disable it for
only the atags_to_fdt bits.

Change-Id: Ib1f66cc4083b4f04d713c3c70610b8a337a6b0ff
Suggested-by: zhxihu <zhxihu@marvell.com>
Signed-off-by: Kees Cook <keescook@chromium.org>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
(cherry picked from commit 7f66cd3f5420e7d11abd234033e7cb7a9738fc38)

UPSTREAM: clk: rockchip: add clock controller for rk3128

Add the clock tree definition for the new rk3128 SoC.
And it also applies to the RK3126 SoC.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from git.kernel.org mmind/linux-rockchip.git v4.13-clk/next
 commit f6022e88faca1a6a21cbd0f009b477bc530b9cc7)

Change-Id: Ib933e398bc8e40d8659bc1cdc419116f48f6ae30
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

UPSTREAM: clk: rockchip: add dt-binding header for rk3128

Add the dt-bindings header for the rk3128,
that gets shared between the clock controller and
the clock references in the dts.
Add softreset ID for rk3128.
And it also applies to the RK3126 SoC.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from git.kernel.org mmind/linux-rockchip.git v4.13-clk/next
 commit b20841b9e0d730206de6ee95f4d00e3f8815ad50)

Change-Id: I70c055570319abe4547ac2a42b9139c7248abb13
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

UPSTREAM: dt-bindings: add bindings for rk3128 clock controller

Add devicetree bindings for Rockchip cru which found on
Rockchip SoCs.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from git.kernel.org mmind/linux-rockchip.git v4.13-clk/next
 commit de2ddc3b694d4594d922534db19e15fc39a3fcee)

Change-Id: I7ee66379d024020a9f8bcc98c3d9c4341391cccd
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

OP-TEE: fix warning when LPAE is activated on ARM

When LPAE is activated, the dma_addr_t type is u64,
but pointer is still 32bit on arm32 platform.
1. %pad is used to print dma_addr_t type in log.
2. The member paddr(dma_addr_t type) in struct shm is cast
to unsigned long when it needs to be cast to a pointer. The cast
is fine as the value of paddr in struct shm is always less than 4G.

Change-Id: I1e2112796f657759dfa845258ea19558cb84c4ec
Signed-off-by: Zhang Zhijie <zhangzj@rock-chips.com>

fiq debugger: rockchip: fix crash because of invalid sp_el0

(1) use cpu id from bl31 delivers;
(2) sp_el0 should point to kernel address in EL1 mode.

On ARM64, kernel uses sp_el0 to store current_thread_info(),
we see a problem: when fiq occurs, cpu is EL1 mode but sp_el0
point to userspace address. At this moment, if we read
'current_thread_info()->cpu' or other, it leads an error.

We find above situation happens when save/restore cpu context
between system mode and user mode under heavy load.
Like 'ret_fast_syscall()', kernel restore context of user mode,
but fiq occurs before the instruction 'eret', so this causes the
above situation.

Assembly code:

ffffff80080826c8 <ret_fast_syscall>:

...skipping...

ffffff80080826fc:       d503201f        nop
ffffff8008082700:       d5384100        mrs     x0, sp_el0
ffffff8008082704:       f9400c00        ldr     x0, [x0,#24]
ffffff8008082708:       d5182000        msr     ttbr0_el1, x0
ffffff800808270c:       d5033fdf        isb
ffffff8008082710:       f9407ff7        ldr     x23, [sp,#248]
ffffff8008082714:       d5184117        msr     sp_el0, x23
ffffff8008082718:       d503201f        nop
ffffff800808271c:       d503201f        nop
ffffff8008082720:       d5184035        msr     elr_el1, x21
ffffff8008082724:       d5184016        msr     spsr_el1, x22
ffffff8008082728:       a94007e0        ldp     x0, x1, [sp]
ffffff800808272c:       a9410fe2        ldp     x2, x3, [sp,#16]
ffffff8008082730:       a94217e4        ldp     x4, x5, [sp,#32]
ffffff8008082734:       a9431fe6        ldp     x6, x7, [sp,#48]
ffffff8008082738:       a94427e8        ldp     x8, x9, [sp,#64]
ffffff800808273c:       a9452fea        ldp     x10, x11, [sp,#80]
ffffff8008082740:       a94637ec        ldp     x12, x13, [sp,#96]
ffffff8008082744:       a9473fee        ldp     x14, x15, [sp,#112]
ffffff8008082748:       a94847f0        ldp     x16, x17, [sp,#128]
ffffff800808274c:       a9494ff2        ldp     x18, x19, [sp,#144]
ffffff8008082750:       a94a57f4        ldp     x20, x21, [sp,#160]
ffffff8008082754:       a94b5ff6        ldp     x22, x23, [sp,#176]
ffffff8008082758:       a94c67f8        ldp     x24, x25, [sp,#192]
ffffff800808275c:       a94d6ffa        ldp     x26, x27, [sp,#208]
ffffff8008082760:       a94e77fc        ldp     x28, x29, [sp,#224]
ffffff8008082764:       f9407bfe        ldr     x30, [sp,#240]
ffffff8008082768:       9104c3ff        add     sp, sp, #0x130
ffffff800808276c:       d69f03e0        eret

Change-Id: I071e899f8a407764e166ca0403199c9d87d6ce78
Signed-off-by: chenjh <chenjh@rock-chips.com>

firmware: rockchip: use sp_el1 from bl31 delivers

we think 'if (fiq_pt_regs.pstate & 0x10)' doesn't make any
sense, use sp_el1 from bl31 delivers is ok.

Change-Id: I0792d76e39912b4ca5484b029761daac05cd719b
Signed-off-by: chenjh <chenjh@rock-chips.com>

ARM64: dts: rk3328-evb: enable hdmi

Change-Id: I42b74009d0ddded9afc10b24e453ca26808bd18e
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>

ARM64: dts: rk3328: add hdmi display node

Change-Id: Ie4821b0c5e49c7b4ee083a2250a71f8ee3edb4e1
Signed-off-by: xuhuicong <xhc@rock-chips.com>
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>

arm64: rockchip_linux_defconfig: update by savedefconfig

Change-Id: I9fc62405d5fad1979d35ada78249a388b0a547dd
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>

ARM: rockchip_linux_defconfig: update by savedefconfig

Change-Id: I2b1de1cd8ee600e593d41cdad0516703d6c94558
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>

ARM: rockchip_defconfig: update by savedefconfig

Change-Id: I5503f37643bd7b9cd0b80a3afbd9e0293608d0cd
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>

arm64: rockchip_defconfig: update by savedefconfig

ROCKCHIP_CPUINFO is default y now.

Change-Id: I4d56e98265ceac3dc071c440a61fbffc736120c6
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>

drm/rockchip: hdmi: support RK3328

Change-Id: I7d93f0d494f6824b0b6e2f82c2c1a57342ea551e
Signed-off-by: Hans Yang <yhx@rock-chips.com>
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>

clk: rockchip: rk3328: add more flags for dclk_lcdc

Add CLK_SET_RATE_PARENT and CLK_SET_RATE_NO_REPARENT
for dclk_lcdc.

Change-Id: I19a4a8e5f9e2cc5fda8b70f1b632dccd538e02a0
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>

ARM64: dts: rockchip: add cpu version in cpuinfo for rk3328

Change-Id: Ief9dd80db35b7b55285b6773f270893a66da5f9d
Signed-off-by: Liang Chen <cl@rock-chips.com>

soc: rockchip: cpuinfo: read cpu version from eFuse

Change-Id: Ia18ff4e745f09fa04690bb7bc6d95169c389b9d2
Signed-off-by: Liang Chen <cl@rock-chips.com>

optee: fix mutex_unlock after mutex_lock

Change-Id: Ic5a4b5b4691b11083e5fd9e327fc4be82d626bfb
Signed-off-by: sean.huang <sean.huang@rock-chips.com>

drm: bridge: dw-hdmi: fixup kernel crash when reboot with hdmi connected

when other devices bind failed,drm will unbind and re-bind all devices.
if don't cancel the delayed work but flush and destroy workqueue directly,
kernel point is likely to become NULL.

Change-Id: Ib48704186ee298cbd4daac1cdbbac5fb3906b6bb
Signed-off-by: algea.cao <algea.cao@rock-chips.com>

usb: dwc_otg_310: pcd: fix force device mode issue

When tested usb device through force device mode method,
we found that usb device failed to connect to usb host
in the following case.

1. Use micro usb 2.0 OTG interface.
2. Plug in otg cable, and the id pin was pulled down
   to Ground.
3. User space force usb to enter device mode through
   'echo 2 > /sys/bus/platform/drivers/usb20_otg/force_usb_mode'
4. Use usb 2.0 Standard-A to Standard-A cable assembly,
   plug into otg cable receptor on one side, and connect
   to PC on the other side.
5. PC fail to enumerate our device, because of usb driver
   logical issue.

This is because that the dwc_otg_pcd_check_vbus_work()
only enable usb to start connecting if check the bvalid
and iddig is high. But in the above test case, the iddig
is low, so fail to start connection work. In this patch,
we enable usb to connect if iddig is high or usb is in
force device mode.

In addition, fix some coding style to increase the readability.

Change-Id: I08f1a4e6e7e5fb246b1716a20d4572d8b866f238
Signed-off-by: William Wu <william.wu@rock-chips.com>

ARM: rockchip: select ARCH_DMA_ADDR_T_64BIT for LPAE

Rockchip RK3288 has some 64-bit capable DMA and therefore needs
dma_addr_t to be a 64-bit size. One user is the Mali GPU.

Change-Id: I47335415fb101b377c408a2631ce211cb3ae3bd8
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>

ARM: rockchip: enable ZONE_DMA for non 64-bit capable peripherals

Most IP cores on ARM Rockchip platforms can only address 32 bits of
physical memory for DMA. Thus ZONE_DMA should be enabled when LPAE
is activated.

Change-Id: I3fce3e01ba31270f066f49bc14fc2078c70d83ea
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>