Saleem Abdulrasool [Sat, 12 Jul 2014 20:49:13 +0000 (20:49 +0000)]
MC: remove use of unnecessary variable
Due to the fact that the windows unwinding has the concept of chained frames, we
maintain a current frame info pointer that is adjusted on any push and pop of a
unwinding context. This just removes an unnecessary variable that was used to
mirror the DWARF unwinding code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212882
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Saleem Abdulrasool [Sat, 12 Jul 2014 20:49:09 +0000 (20:49 +0000)]
MC: rename MCW64UnwindInfo to MCWinFrameInfo
This structure contains information related to the call frame used to generate
unwinding information. Rename this to reflect the future use to represent the
shared state between various architectures for WinCFI information.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212881
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Simon Atanasyan [Sat, 12 Jul 2014 18:25:08 +0000 (18:25 +0000)]
[ELFYAML] Group ELF section type flags to target specific blocks.
Recognize only flags which correspond to the current target.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212880
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Owen Anderson [Sat, 12 Jul 2014 07:12:47 +0000 (07:12 +0000)]
Fix an issue with the MergeBasicBlockIntoOnlyPred() helper function where it did
not properly handle the case where the predecessor block was the entry block to
the function. The only in-tree client of this is JumpThreading, which worked
around the issue in its own code. This patch moves the solution into the helper
so that JumpThreading (and other clients) do not have to replicate the same fix
everywhere.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212875
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Alexey Samsonov [Sat, 12 Jul 2014 00:42:52 +0000 (00:42 +0000)]
[ASan] Collect unmangled names of global variables in Clang to print them in error reports.
Currently ASan instrumentation pass creates a string with global name
for each instrumented global (to include global names in the error report). Global
name is already mangled at this point, and we may not be able to demangle it
at runtime (e.g. there is no __cxa_demangle on Android).
Instead, create a string with fully qualified global name in Clang, and pass it
to ASan instrumentation pass in llvm.asan.globals metadata. If there is no metadata
for some global, ASan will use the original algorithm.
This fixes https://code.google.com/p/address-sanitizer/issues/detail?id=264.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212872
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Matt Arsenault [Sat, 12 Jul 2014 00:36:19 +0000 (00:36 +0000)]
R600: Add missing tests for some intrinsics
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212870
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Duncan P. N. Exon Smith [Sat, 12 Jul 2014 00:26:00 +0000 (00:26 +0000)]
BFI: Add constructor for Weight
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212868
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Duncan P. N. Exon Smith [Sat, 12 Jul 2014 00:21:30 +0000 (00:21 +0000)]
BFI: Clean up BlockMass
Implementation is small now -- the interesting logic was moved to
`BranchProbability` a while ago. Move it into `bfi_detail` and get rid
of the related TODOs.
I was originally planning to define it within `BlockFrequencyInfoImpl`
(or `BFIIBase`), but it seems cleaner in a namespace. Besides,
`isPodLike` needs to be specialized before `BlockMass` can be used in
some of the other data structures, and there isn't a clear way to do
that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212866
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Reid Kleckner [Sat, 12 Jul 2014 00:18:58 +0000 (00:18 +0000)]
Option: Propagate flags from groups to options in each group
This should make it easy to set a flag for a whole group of clang driver
options.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212865
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Lang Hames [Sat, 12 Jul 2014 00:16:47 +0000 (00:16 +0000)]
[RuntimeDyld] Fix stub size and offset for AArch64 in RuntimeDyldMachO.h.
<rdar://problem/
17648000>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212864
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Reid Kleckner [Sat, 12 Jul 2014 00:06:46 +0000 (00:06 +0000)]
Avoid a warning from MSVC on "*/" in this code by inserting a space
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212862
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Duncan P. N. Exon Smith [Fri, 11 Jul 2014 23:56:50 +0000 (23:56 +0000)]
BFI: Mark the end of namespaces
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212861
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Lang Hames [Fri, 11 Jul 2014 23:52:07 +0000 (23:52 +0000)]
[RuntimeDyld] Add GOT support for AArch64 to RuntimeDyldMachO.
Test cases to follow once RuntimeDyldChecker supports introspection of stubs.
Fixes <rdar://problem/
17648000>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212859
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Juergen Ributzka [Fri, 11 Jul 2014 23:10:08 +0000 (23:10 +0000)]
Revert "[FastISel][X86] Implement the FastLowerIntrinsicCall hook."
This reverts commit r212851, because it broke the memset lowering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212855
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Juergen Ributzka [Fri, 11 Jul 2014 22:37:43 +0000 (22:37 +0000)]
[FastISel][X86] Implement the FastLowerIntrinsicCall hook.
Rename X86VisitIntrinsicCall -> FastLowerIntrinsicCall, which effectively
implements the target hook.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212851
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Alexey Samsonov [Fri, 11 Jul 2014 22:36:02 +0000 (22:36 +0000)]
[ASan] Introduce a struct representing the layout of metadata entry in llvm.asan.globals.
No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212850
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Juergen Ributzka [Fri, 11 Jul 2014 22:19:02 +0000 (22:19 +0000)]
[FastISel] Add target-independent patchpoint intrinsic support. WIP.
This implements the target-independent lowering for the patchpoint
intrinsic. Targets have to implement the FastLowerCall
hook to support this intrinsic.
Related to <rdar://problem/
17427052>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212849
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Juergen Ributzka [Fri, 11 Jul 2014 22:01:42 +0000 (22:01 +0000)]
[FastISel] Add basic infrastructure to support a target-independent call lowering hook in FastISel. WIP
The infrastructure mimics the call lowering we have already in place for
SelectionDAG, but with limitations. For example structure return demotion and
non-simple types are not supported (yet).
Currently every backend has its own implementation and duplicated code for call
lowering. There is also no specified interface that could be called from
target-independent code. The target-hook is opt-in and doesn't affect current
implementations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212848
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Aditya Nandakumar [Fri, 11 Jul 2014 21:49:39 +0000 (21:49 +0000)]
When we sink an instruction, this can open up opportunity for the operands to be sunk - add them to the worklist
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212847
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Argyrios Kyrtzidis [Fri, 11 Jul 2014 21:44:54 +0000 (21:44 +0000)]
Move the API and implementation of clang::driver::getARMCPUForMArch() to llvm::Triple::getARMCPUForArch().
Suggested by Eric Christopher.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212846
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Juergen Ributzka [Fri, 11 Jul 2014 20:50:47 +0000 (20:50 +0000)]
[FastISel] Make isInTailCallPosition independent of SelectionDAG.
Break out the arguemnts required from SelectionDAG, so that this function can
also be used by FastISel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212844
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Juergen Ributzka [Fri, 11 Jul 2014 20:42:12 +0000 (20:42 +0000)]
[FastISel] Breakout intrinsic lowering into a separate function and add a target-hook.
Create a separate helper function for target-independent intrinsic lowering. Also
add an target-hook that allows to directly call into a target-sepcific intrinsic
lowering method. Currently the implementation is opt-in and doesn't affect
existing target implementations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212843
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Kevin Enderby [Fri, 11 Jul 2014 20:30:00 +0000 (20:30 +0000)]
Add the "-s" flag to llvm-nm for Mach-O files that prints symbols only in
the specified section. This is same functionality as darwin’s nm(1) "-s" flag.
There is one FIXME in the code and I’m all ears to anyone that can help me
with that. This option takes exactly two strings and should be allowed
anywhere on the command line. Such that "llvm-nm -s __TEXT __text foo.o"
would work. But that does not as the CommandLine Library does not have a
way to make this work as far as I can tell. For now the "-s __TEXT __text"
has to be last on the command line.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212842
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Alp Toker [Fri, 11 Jul 2014 18:23:08 +0000 (18:23 +0000)]
Simplify the raw_svector_ostream tweak from r212816
The memcpy() and overlap helps didn't help much with timings, so clean up the change.
The difference at this point is that we now leave growth of the storage buffer
up to SmallVector's implementation:
- OS.reserve(OS.capacity() * 2);
+ OS.reserve(OS.size() + 64);
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212837
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Ulrich Weigand [Fri, 11 Jul 2014 17:34:44 +0000 (17:34 +0000)]
[MC] Constify MCELF::GetVisibility and MCELF::getOther
These two routines didn't take a "const MCSymbolData &SD"
like the other MCELF::Get routines for some reason ...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212834
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Ulrich Weigand [Fri, 11 Jul 2014 17:19:31 +0000 (17:19 +0000)]
[PowerPC] Fix invalid displacement created by LocalStackAlloc
This commit fixes a bug in PPCRegisterInfo::isFrameOffsetLegal that
could result in the LocalStackAlloc pass creating an MI instruction
out-of-range displacement:
%vreg17<def> = LD 33184, %vreg31; mem:LD8[%g](align=32)
%G8RC:%vreg17 G8RC_and_G8RC_NOX0:%vreg31
(In final assembler output the top bits are stripped off, resulting
in a negative offset loading from below the stack pointer.)
Common code expects the isFrameOffsetLegal routine to verify whether
adding a given offset to the offset already present in the instruction
results in a valid displacement. However, on PowerPC the routine
did not take the already present instruction offset into account.
This commit fixes isFrameOffsetLegal to add the instruction offset,
and updates a local caller (needsFrameBaseReg) to no longer add the
instruction offset itself before calling isFrameOffsetLegal.
Reviewed by Hal Finkel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212832
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Marek Olsak [Fri, 11 Jul 2014 17:11:52 +0000 (17:11 +0000)]
R600/SI: Use i32 vectors for resources and samplers
This affects new intrinsics only.
What surprises me is that v32i8 still works.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212831
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Marek Olsak [Fri, 11 Jul 2014 17:11:46 +0000 (17:11 +0000)]
R600/SI: add sample and image intrinsics exposing all instruction fields
We need the intrinsics with offsets, so why not just add them all.
The R128 parameter will also be useful for reducing SGPR usage.
GL_ARB_image_load_store also adds some image GLSL modifiers like "coherent",
so Mesa will probably translate those to slc, glc, etc.
When LLVM 3.5 is released, I'll switch Mesa to these new intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212830
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Marek Olsak [Fri, 11 Jul 2014 17:11:39 +0000 (17:11 +0000)]
R600/SI: fix shadow mapping for 1D and 2D array textures
It was conflicting with def TEX_SHADOW_ARRAY, which also handles them.
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212829
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Timur Iskhodzhanov [Fri, 11 Jul 2014 16:32:53 +0000 (16:32 +0000)]
Add a test case for r212596
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212828
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NAKAMURA Takumi [Fri, 11 Jul 2014 14:44:10 +0000 (14:44 +0000)]
llvm/test/BugPoint/compile-custom.ll: Use explicit %python to invoke a test script, compile-custom.ll.py, for shebang-incapable hosts.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212820
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NAKAMURA Takumi [Fri, 11 Jul 2014 14:36:39 +0000 (14:36 +0000)]
llvm/test/lit.cfg: Let %python available.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212819
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NAKAMURA Takumi [Fri, 11 Jul 2014 14:36:28 +0000 (14:36 +0000)]
[CMake] add_llvm_library: Add "RUNTIME DESTINATION bin" to install(). It affects add_library(SHARED) for Win32.DLL.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212818
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Alp Toker [Fri, 11 Jul 2014 14:02:04 +0000 (14:02 +0000)]
raw_svector_ostream: grow and reserve atomically
Including the scratch buffer size in the initial reservation eliminates the
subsequent malloc+move operation and offers a healthier constant growth with
less memory wastage.
When doing this, take care to avoid invalidating the source buffer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212816
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Oliver Stannard [Fri, 11 Jul 2014 13:33:46 +0000 (13:33 +0000)]
ARM: Allow __fp16 as a function arg or return type for AArch64
ACLE 2.0 allows __fp16 to be used as a function argument or return
type. This enables this for AArch64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212812
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Alexander Kornienko [Fri, 11 Jul 2014 12:39:32 +0000 (12:39 +0000)]
Add FileCheck -implicit-check-not option to allow stricter tests without adding too many CHECK-NOTs manually.
Summary:
Add FileCheck -implicit-check-not option which allows specifying a
pattern that should only occur in the input when explicitly matched by a
positive check. This feature allows checking tool diagnostics in a way
clang -verify does it for compiler diagnostics.
The option has been tested on a number of clang-tidy checks, I'll post a link to
the clang-tidy patch to this thread.
Once there's an agreement on the general direction, I can add tests and
documentation.
Reviewers: djasper, bkramer
Reviewed By: bkramer
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D4462
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212810
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Quentin Colombet [Fri, 11 Jul 2014 12:08:23 +0000 (12:08 +0000)]
[X86] Fix the inversion of low and high bits for the lowering of MUL_LOHI.
Also add a few comments.
<rdar://problem/
17581756>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212808
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Marcello Maggioni [Fri, 11 Jul 2014 10:36:00 +0000 (10:36 +0000)]
Added test for commit r212802 that was missing
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212803
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Marcello Maggioni [Fri, 11 Jul 2014 10:34:36 +0000 (10:34 +0000)]
Fixup PHIs in LowerSwitch when a Leaf node is not emitted.
This commit fixes bug http://llvm.org/bugs/show_bug.cgi?id=20103.
Thanks to Qwertyuiop for the report and the proposed fix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212802
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Adam Nemet [Fri, 11 Jul 2014 05:23:25 +0000 (05:23 +0000)]
[X86] AVX512: Improve readability of isCDisp8
No functional change. As I was trying to understand this function, I found
that variables were reused with confusing names and the broadcast case was a
bit too implicit. Hopefully, this is an improvement.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212795
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Adam Nemet [Fri, 11 Jul 2014 05:23:12 +0000 (05:23 +0000)]
[X86] AVX512: Simplify logic in isCDisp8
It was computing the VL/n case as:
MemObjSize = VectorByteSize / ElemByteSize / Divider * ElemByteSize
ElemByteSize not only falls out but VectorByteSize/Divider now actually
matches the definition of VL/n.
Also some formatting fixes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212794
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David Blaikie [Fri, 11 Jul 2014 02:42:57 +0000 (02:42 +0000)]
Revert "Reapply "DebugInfo: Ensure that all debug location scope chains from instructions within a function, lead to the function itself.""
This reverts commit r212776.
Nope, still seems to be failing on the sanitizer bots... but hey, not
the msan self-host anymore, it's failing in asan now. I'll start looking
there next.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212793
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Mark Heffernan [Thu, 10 Jul 2014 23:30:06 +0000 (23:30 +0000)]
Partially fix PR20058: reduce compile time for loop unrolling with very high count by reducing calls to SE->forgetLoop
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212782
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Lang Hames [Thu, 10 Jul 2014 23:29:11 +0000 (23:29 +0000)]
[RuntimeDyld] Replace a crufty old ARM RuntimeDyld test with a new one that uses
RuntimeDyldChecker.
This allows us to remove one of the six remaining object files in the LLVM
source tree.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212780
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Lang Hames [Thu, 10 Jul 2014 23:26:20 +0000 (23:26 +0000)]
[RuntimeDyld] Improve error diagnostic in RuntimeDyldChecker.
The compiler often emits assembler-local labels (beginning with 'L') for use in
relocation expressions, however these aren't included in the object files.
Teach RuntimeDyldChecker to warn the user if they try to use one of these in an
expression, since it will never work.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212777
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David Blaikie [Thu, 10 Jul 2014 22:59:39 +0000 (22:59 +0000)]
Reapply "DebugInfo: Ensure that all debug location scope chains from instructions within a function, lead to the function itself."
Committed in r212205 and reverted in r212226 due to msan self-hosting
failure, I believe I've got that fixed by r212761 to Clang.
Original commit message:
"Originally committed in r211723, reverted in r211724 due to failure
cases found and fixed (ArgumentPromotion: r211872, Inlining: r212065),
committed again in r212085 and reverted again in r212089 after fixing
some other cases, such as debug info subprogram lists not keeping track
of the function they represent (r212128) and then short-circuiting
things like LiveDebugVariables that build LexicalScopes for functions
that might not have full debug info.
And again, I believe the invariant actually holds for some reasonable
amount of code (but I'll keep an eye on the buildbots and see what
happens... ).
Original commit message:
PR20038: DebugInfo: Inlined call sites where the caller has debug info
but the call itself has no debug location.
This situation does bad things when inlined, so I've fixed Clang not to
produce inlinable call sites without locations when the caller has debug
info (in the one case where I could find that this occurred). This
updates the PR20038 test case to be what clang now produces, and readds
the assertion that had to be removed due to this bug.
I've also beefed up the debug info verifier to help diagnose these
issues in the future, and I hope to add checks to the inliner to just
assert-fail if it encounters this situation. If, in the future, we
decide we have to cope with this situation, the right thing to do is
probably to just remove all the DebugLocs from the inlined
instructions."
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212776
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David Blaikie [Thu, 10 Jul 2014 22:57:40 +0000 (22:57 +0000)]
This test case doesn't actually need the inliner to reproduce the input.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212775
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Jan Vesely [Thu, 10 Jul 2014 22:40:21 +0000 (22:40 +0000)]
R600: Implement float to long/ulong
Use alg. from LegalizeDAG.cpp
Move Expand setting to SIISellowering
v2: Extend existing tests instead of creating new ones
v3: use separate LowerFPTOSINT function
v4: use TargetLowering::expandFP_TO_SINT
add comment about using FP_TO_SINT for uints
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Reviewed-by: Tom Stellard <tom@stellard.net>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212773
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Jan Vesely [Thu, 10 Jul 2014 22:40:18 +0000 (22:40 +0000)]
SelectionDAG: Factor FP_TO_SINT lower code out of DAGLegalizer
Move the code to a helper function to allow calls from TypeLegalizer.
No functionality change intended
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Reviewed-by: Tom Stellard <tom@stellard.net>
Reviewed-by: Owen Anderson <resistor@mac.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212772
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Brad Smith [Thu, 10 Jul 2014 22:37:28 +0000 (22:37 +0000)]
Use the integrated assembler by default on OpenBSD.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212771
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Zoran Jovanovic [Thu, 10 Jul 2014 22:23:30 +0000 (22:23 +0000)]
[mips] Emit two CFI offset directives per double precision SDC1/LDC1
instead of just one for FR=1 registers
Differential Revision: http://reviews.llvm.org/D4310
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212769
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Andrea Di Biagio [Thu, 10 Jul 2014 18:59:41 +0000 (18:59 +0000)]
Extend the test coverage in combine-vec-shuffle-2.ll adding some negative tests.
Add test cases where we don't expect to trigger the combine optimizations
introduced at revision 212748.
No functional change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212756
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Matt Arsenault [Thu, 10 Jul 2014 18:21:04 +0000 (18:21 +0000)]
Revert "Revert r212640, "Add trunc (select c, a, b) -> select c (trunc a), (trunc b) combine.""
Don't try to convert the select condition type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212750
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Andrea Di Biagio [Thu, 10 Jul 2014 18:04:55 +0000 (18:04 +0000)]
[DAG] Further improve the logic in DAGCombiner that folds a pair of shuffles into a single shuffle if the resulting mask is legal.
This patch teaches the DAGCombiner how to fold shuffles according to the
following new rules:
1. shuffle(shuffle(x, y), undef) -> x
2. shuffle(shuffle(x, y), undef) -> y
3. shuffle(shuffle(x, y), undef) -> shuffle(x, undef)
4. shuffle(shuffle(x, y), undef) -> shuffle(y, undef)
The backend avoids to combine shuffles according to rules 3. and 4. if
the resulting shuffle does not have a legal mask. This is to avoid introducing
illegal shuffles that are potentially expanded into a sub-optimal sequence of
target specific dag nodes during vector legalization.
Added test case combine-vec-shuffle-2.ll to verify that we correctly triggers
the new rules when combining shuffles.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212748
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Akira Hatanaka [Thu, 10 Jul 2014 18:00:53 +0000 (18:00 +0000)]
[X86] Mark pseudo instruction TEST8ri_NOEREX as hasSIdeEffects=0.
Also, add a case clause in X86InstrInfo::shouldScheduleAdjacent to enable
macro-fusion.
<rdar://problem/
15680770>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212747
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Eric Christopher [Thu, 10 Jul 2014 17:26:54 +0000 (17:26 +0000)]
Add the CSR company and the Kalimba DSP processor to Triple.
Patch by Matthew Gardiner with fixes by me.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212745
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Eric Christopher [Thu, 10 Jul 2014 17:26:51 +0000 (17:26 +0000)]
Make it possible for the Subtarget to change between function
passes in the mips back end. This, unfortunately, required a
bit of churn in the various predicates to use a pointer rather
than a reference.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212744
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Duncan P. N. Exon Smith [Thu, 10 Jul 2014 17:13:27 +0000 (17:13 +0000)]
InstCombine: Fix a crash in Descale for multiply-by-zero
Fix a crash in `InstCombiner::Descale()` when a multiply-by-zero gets
created as an argument to a GEP partway through an iteration, causing
-instcombine to optimize the GEP before the multiply.
rdar://problem/
17615671
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212742
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David Majnemer [Thu, 10 Jul 2014 16:26:10 +0000 (16:26 +0000)]
IR: Aliases don't belong to an explicit comdat
Aliases inherit their comdat from their aliasee, they don't have an
explicit comdat.
This fixes PR20279.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212732
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Hal Finkel [Thu, 10 Jul 2014 16:07:11 +0000 (16:07 +0000)]
Feeding isSafeToSpeculativelyExecute its DataLayout pointer (in Sink)
This is the one remaining place I see where passing
isSafeToSpeculativelyExecute a DataLayout pointer might matter (at least for
loads) -- I think I got the others in r212720. Most of the other remaining
callers of isSafeToSpeculativelyExecute only use it for call sites (or
otherwise exclude loads).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212730
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David Majnemer [Thu, 10 Jul 2014 16:04:04 +0000 (16:04 +0000)]
Mips: Silence a -Wcovered-switch-default
Remove a default label which covered no enumerators, replace it with a
llvm_unreachable.
No functionality changed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212729
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Zoran Jovanovic [Thu, 10 Jul 2014 15:36:12 +0000 (15:36 +0000)]
[mips] Added FPXX modeless calling convention.
Differential Revision: http://reviews.llvm.org/D4293
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212726
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Arnaud A. de Grandmaison [Thu, 10 Jul 2014 15:12:26 +0000 (15:12 +0000)]
[AArch64] Add logical alias instructions to MC AsmParser
This patch teaches the AsmParser to accept some logical+immediate
instructions and convert them as shown:
bic Rd, Rn, #imm -> and Rd, Rn, #~imm
bics Rd, Rn, #imm -> ands Rd, Rn, #~imm
orn Rd, Rn, #imm -> orr Rd, Rn, #~imm
eon Rd, Rn, #imm -> eor Rd, Rn, #~imm
Those instructions are an alternate syntax available to assembly coders,
and are needed in order to support code already compiling with some other
assemblers. For example, the bic construct is used by the linux kernel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212722
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Hal Finkel [Thu, 10 Jul 2014 14:41:31 +0000 (14:41 +0000)]
Feeding isSafeToSpeculativelyExecute its DataLayout pointer
isSafeToSpeculativelyExecute can optionally take a DataLayout pointer. In the
past, this was mainly used to make better decisions regarding divisions known
not to trap, and so was not all that important for users concerned with "cheap"
instructions. However, now it also helps look through bitcasts for
dereferencable loads, and will also be important if/when we add a
dereferencable pointer attribute.
This is some initial work to feed a DataLayout pointer through to callers of
isSafeToSpeculativelyExecute, generally where one was already available.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212720
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Tim Northover [Thu, 10 Jul 2014 14:18:46 +0000 (14:18 +0000)]
AArch64: correctly fast-isel i8 & i16 multiplies
We were asking for a register for type i8 or i16 which caused an assert.
rdar://problem/
17620015
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212718
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Daniel Sanders [Thu, 10 Jul 2014 13:38:23 +0000 (13:38 +0000)]
[mips] Add support for -modd-spreg/-mno-odd-spreg
Summary:
When -mno-odd-spreg is in effect, 32-bit floating point values are not
permitted in odd FPU registers. The option also prohibits 32-bit and 64-bit
floating point comparison results from being written to odd registers.
This option has three purposes:
* It allows support for certain MIPS implementations such as loongson-3a that
do not allow the use of odd registers for single precision arithmetic.
* When using -mfpxx, -mno-odd-spreg is the default and this allows us to
statically check that code is compliant with the O32 FPXX ABI since mtc1/mfc1
instructions to/from odd registers are guaranteed not to appear for any
reason. Once this has been established, the user can then re-enable
-modd-spreg to regain the use of all 32 single-precision registers.
* When using -mfp64 and -mno-odd-spreg together, an O32 extension named
O32 FP64A is used as the ABI. This is intended to provide almost all
functionality of an FR=1 processor but can also be executed on a FR=0 core
with the assistance of a hardware compatibility mode which emulates FR=0
behaviour on an FR=1 processor.
* Added '.module oddspreg' and '.module nooddspreg' each of which update
the .MIPS.abiflags section appropriately
* Moved setFpABI() call inside emitDirectiveModuleFP() so that the caller
doesn't have to remember to do it.
* MipsABIFlags now calculates the flags1 and flags2 member on demand rather
than trying to maintain them in the same format they will be emitted in.
There is one portion of the -mfp64 and -mno-odd-spreg combination that is not
implemented yet. Moves to/from odd-numbered double-precision registers must not
use mtc1. I will fix this in a follow-up.
Differential Revision: http://reviews.llvm.org/D4383
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212717
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Zinovy Nis [Thu, 10 Jul 2014 13:03:26 +0000 (13:03 +0000)]
[x32] Add AsmBackend for X32 which uses ELF32 with x86_64 (the author is Pavel Chupin).
This is minimal change for backend required to have "hello world" compiled and working on x32 target (x86_64-linux-gnux32). More patches for x32 will follow.
Differential Revision: http://reviews.llvm.org/D4181
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212716
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Chandler Carruth [Thu, 10 Jul 2014 12:32:32 +0000 (12:32 +0000)]
[x86,SDAG] Introduce any- and sign-extend-vector-inreg nodes analogous
to the zero-extend-vector-inreg node introduced previously for the same
purpose: manage the type legalization of widened extend operations,
especially to support the experimental widening mode for x86.
I'm adding both because sign-extend is expanded in terms of any-extend
with shifts to propagate the sign bit. This removes the last
fundamental scalarization from vec_cast2.ll (a test case that hit many
really bad edge cases for widening legalization), although the trunc
tests in that file still appear scalarized because the the shuffle
legalization is scalarizing. Funny thing, I've been working on that.
Some initial experiments with this and SSE2 scenarios is showing
moderately good behavior already for sign extension. Still some work to
do on the shuffle combining on X86 before we're generating optimal
sequences, but avoiding scalarization is a huge step forward.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212714
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Richard Sandiford [Thu, 10 Jul 2014 11:44:37 +0000 (11:44 +0000)]
[SystemZ] Use SystemZCallingConv.td to define callee-saved registers
Just a clean-up. No behavioral change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212711
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NAKAMURA Takumi [Thu, 10 Jul 2014 11:39:59 +0000 (11:39 +0000)]
SpecialCaseList.h: Fix -Wdocumentation with \code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212710
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NAKAMURA Takumi [Thu, 10 Jul 2014 11:37:39 +0000 (11:37 +0000)]
llvm/test/CodeGen/X86/shift-parts.ll: FileCheck-ize. (from r212640)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212709
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NAKAMURA Takumi [Thu, 10 Jul 2014 11:37:28 +0000 (11:37 +0000)]
Revert r212640, "Add trunc (select c, a, b) -> select c (trunc a), (trunc b) combine."
This caused miscompilation on, at least, x86-64. SExt(i1 cond) confused other optimizations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212708
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Richard Sandiford [Thu, 10 Jul 2014 11:29:23 +0000 (11:29 +0000)]
[SystemZ] Tweak instruction format classifications
There's no real need to have Shift as a separate format type from Binary.
The comments for other format types were too specific and in some cases
no longer accurate.
Just a clean-up, no behavioral change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212707
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Chandler Carruth [Thu, 10 Jul 2014 11:09:29 +0000 (11:09 +0000)]
[x86] Add another combine that is particularly useful for the new vector
shuffle lowering: match shuffle patterns equivalent to an unpcklwd or
unpckhwd instruction.
This allows us to use generic lowering code for v8i16 shuffles and match
the unpack pattern late.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212705
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Richard Sandiford [Thu, 10 Jul 2014 11:00:55 +0000 (11:00 +0000)]
[SystemZ] Add MC support for LEDBRA, LEXBRA and LDXBRA
These instructions aren't used for codegen since the original L*DB instructions
are suitable for fround.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212703
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Richard Sandiford [Thu, 10 Jul 2014 10:52:51 +0000 (10:52 +0000)]
[SystemZ] Avoid using i8 constants for immediate fields
Immediate fields that have no natural MVT type tended to use i8 if the
field was small enough. This was a bit confusing since i8 isn't a legal
type for the target. Fields for short immediates in a 32-bit or 64-bit
operation use i32 or i64 instead, so it would be better to do the same
for all fields.
No behavioral change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212702
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Richard Sandiford [Thu, 10 Jul 2014 10:45:11 +0000 (10:45 +0000)]
[SystemZ] Fix FPR dwarf numbering
The dwarf FPR numbers are supposed to have the order F0, F2, F4, F6,
F1, F3, F5, F7, F8, etc., which matches the pairing of registers for
long doubles. E.g. a long double stored in F0 is paired with F2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212701
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Daniel Sanders [Thu, 10 Jul 2014 10:18:12 +0000 (10:18 +0000)]
Make it possible for ints/floats to return different values from getBooleanContents()
Summary:
On MIPS32r6/MIPS64r6, floating point comparisons return 0 or -1 but integer
comparisons return 0 or 1.
Updated the various uses of getBooleanContents. Two simplifications had to be
disabled when float and int boolean contents differ:
- ScalarizeVecRes_VSELECT except when the kind of boolean contents is trivially
discoverable (i.e. when the condition of the VSELECT is a SETCC node).
- visitVSELECT (select C, 0, 1) -> (xor C, 1).
Come to think of it, this one could test for the common case of 'C'
being a SETCC too.
Preserved existing behaviour for all other targets and updated the affected
MIPS32r6/MIPS64r6 tests. This also fixes the pi benchmark where the 'low'
variable was counting in the wrong direction because it thought it could simply
add the result of the comparison.
Reviewers: hfinkel
Reviewed By: hfinkel
Subscribers: hfinkel, jholewinski, mcrosier, llvm-commits
Differential Revision: http://reviews.llvm.org/D4389
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212697
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Chandler Carruth [Thu, 10 Jul 2014 09:57:36 +0000 (09:57 +0000)]
[x86] Expand the target DAG combining for PSHUFD nodes to be able to
combine into half-shuffles through unpack instructions that expand the
half to a whole vector without messing with the dword lanes.
This fixes some redundant instructions in splat-like lowerings for
v16i8, which are now getting to be *really* nice.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212695
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Chandler Carruth [Thu, 10 Jul 2014 09:16:40 +0000 (09:16 +0000)]
[x86] Tweak the v16i8 single input special case lowering for shuffles
that splat i8s into i16s.
Previously, we would try much too hard to arrange a sequence of i8s in
one half of the input such that we could unpack them into i16s and
shuffle those into place. This isn't always going to be a cheaper i8
shuffle than our other strategies. The case where it is always going to
be cheaper is when we can arrange all the necessary inputs into one half
using just i16 shuffles. It happens that viewing the problem this way
also makes it much easier to produce an efficient set of shuffles to
move the inputs into one half and then unpack them.
With this, our splat code gets one step closer to being not terrible
with the new experimental lowering strategy. It also exposes two
combines missing which I will add next.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212692
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Hal Finkel [Thu, 10 Jul 2014 07:04:37 +0000 (07:04 +0000)]
A test case for not asserting in isDereferenceablePointer upon unsized types
This is the test case for r212687.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212688
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Hal Finkel [Thu, 10 Jul 2014 06:06:11 +0000 (06:06 +0000)]
Fix isDereferenceablePointer not to try to take the size of an unsized type.
I'll add a test-case shortly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212687
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Hal Finkel [Thu, 10 Jul 2014 05:27:53 +0000 (05:27 +0000)]
Allow isDereferenceablePointer to look through some bitcasts
isDereferenceablePointer should not give up upon encountering any bitcast. If
we're casting from a pointer to a larger type to a pointer to a small type, we
can continue by examining the bitcast's operand. This missing capability
was noted in a comment in the function.
In order for this to work, isDereferenceablePointer now takes an optional
DataLayout pointer (essentially all callers already had such a pointer
available). Most code uses isDereferenceablePointer though
isSafeToSpeculativelyExecute (which already took an optional DataLayout
pointer), and to enable the LICM test case, LICM needs to actually provide its DL
pointer to isSafeToSpeculativelyExecute (which it was not doing previously).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212686
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Saleem Abdulrasool [Thu, 10 Jul 2014 04:50:09 +0000 (04:50 +0000)]
MC: modernise for loop
Convert a for loop to range bsaed form. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212684
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Saleem Abdulrasool [Thu, 10 Jul 2014 04:50:06 +0000 (04:50 +0000)]
MC: add and use an accessor for WinCFI
This adds a utility method to access the WinCFI information in bulk and uses
that to iterate rather than requesting the count and individually iterating
them. This is in preparation for restructuring WinCFI handling to enable more
clear sharing across architectures to enable unwind information emission for
Windows on ARM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212683
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Peter Collingbourne [Thu, 10 Jul 2014 04:39:40 +0000 (04:39 +0000)]
Remove move assignment operator to appease older GCCs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212682
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Chandler Carruth [Thu, 10 Jul 2014 04:34:06 +0000 (04:34 +0000)]
[x86] Initial improvements to the new shuffle lowering for v16i8
shuffles specifically for cases where a small subset of the elements in
the input vector are actually used.
This is specifically targetted at improving the shuffles generated for
trunc operations, but also helps out splat-like operations.
There is still some really low-hanging fruit here that I want to address
but this is a huge step in the right direction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212680
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Peter Collingbourne [Thu, 10 Jul 2014 04:29:06 +0000 (04:29 +0000)]
Explicitly define move constructor and move assignment operator to appease MSVC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212679
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Peter Collingbourne [Thu, 10 Jul 2014 03:55:02 +0000 (03:55 +0000)]
SpecialCaseList: use std::unique_ptr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212678
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Hao Liu [Thu, 10 Jul 2014 03:41:50 +0000 (03:41 +0000)]
[AArch64]Fix an assertion failure in DAG Combiner about concating 2 build_vector.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212677
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Matt Arsenault [Thu, 10 Jul 2014 03:22:20 +0000 (03:22 +0000)]
R600/SI: Add support for llvm.convert.{to|from}.fp16
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212676
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Matt Arsenault [Thu, 10 Jul 2014 03:22:16 +0000 (03:22 +0000)]
Fix types in documentation.
The examples were using f32, but the IR type is called float
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212675
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Chandler Carruth [Thu, 10 Jul 2014 02:24:26 +0000 (02:24 +0000)]
[x86] Refactor some of the new code for lowering v16i8 shuffles to
remove duplication and make it easier to select different strategies.
No functionality changed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212674
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Peter Collingbourne [Thu, 10 Jul 2014 01:30:39 +0000 (01:30 +0000)]
[dfsan] Handle bitcast aliases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212668
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Chandler Carruth [Wed, 9 Jul 2014 22:53:04 +0000 (22:53 +0000)]
[SDAG] Make the new zext-vector-inreg node default to expand so targets
don't need to set it manually.
This is based on feedback from Tom who pointed out that if every target
needs to handle this we need to reach out to those maintainers. In fact,
it doesn't make sense to duplicate everything when anything other than
expand seems unlikely at this stage.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212661
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David Blaikie [Wed, 9 Jul 2014 21:02:41 +0000 (21:02 +0000)]
Recommit r212203: Don't try to construct debug LexicalScopes hierarchy for functions that do not have top level debug information.
Reverted by Eric Christopher (Thanks!) in r212203 after Bob Wilson
reported LTO issues. Duncan Exon Smith and Aditya Nandakumar helped
provide a reduced reproduction, though the failure wasn't too hard to
guess, and even easier with the example to confirm.
The assertion that the subprogram metadata associated with an
llvm::Function matches the scope data referenced by the DbgLocs on the
instructions in that function is not valid under LTO. In LTO, a C++
inline function might exist in multiple CUs and the subprogram metadata
nodes will refer to the same llvm::Function. In this case, depending on
the order of the CUs, the first intance of the subprogram metadata may
not be the one referenced by the instructions in that function and the
assertion will fail.
A test case (test/DebugInfo/cross-cu-linkonce-distinct.ll) is added, the
assertion removed and a comment added to explain this situation.
Original commit message:
If a function isn't actually in a CU's subprogram list in the debug info
metadata, ignore all the DebugLocs and don't try to build scopes, track
variables, etc.
While this is possibly a minor optimization, it's also a correctness fix
for an incoming patch that will add assertions to LexicalScopes and the
debug info verifier to ensure that all scope chains lead to debug info
for the current function.
Fix up a few test cases that had broken/incomplete debug info that could
violate this constraint.
Add a test case where this occurs by design (inlining a
debug-info-having function in an attribute nodebug function - we want
this to work because /if/ the nodebug function is then inlined into a
debug-info-having function, it should be fine (and will work fine - we
just stitch the scopes up as usual), but should the inlining not happen
we need to not assert fail either).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212649
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Alexey Samsonov [Wed, 9 Jul 2014 19:40:08 +0000 (19:40 +0000)]
Decouple llvm::SpecialCaseList text representation and its LLVM IR semantics.
Turn llvm::SpecialCaseList into a simple class that parses text files in
a specified format and knows nothing about LLVM IR. Move this class into
LLVMSupport library. Implement two users of this class:
* DFSanABIList in DFSan instrumentation pass.
* SanitizerBlacklist in Clang CodeGen library.
The latter will be modified to use actual source-level information from frontend
(source file names) instead of unstable LLVM IR things (LLVM Module identifier).
Remove dependency edge from ClangCodeGen/ClangDriver to LLVMTransformUtils.
No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212643
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Tim Northover [Wed, 9 Jul 2014 19:14:34 +0000 (19:14 +0000)]
Use simpler constructor for range adapter.
It is a good idea, it's slightly clearer and simpler. Unfortunately
the headline news is: we save one line!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212641
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Matt Arsenault [Wed, 9 Jul 2014 19:12:07 +0000 (19:12 +0000)]
Add trunc (select c, a, b) -> select c (trunc a), (trunc b) combine.
Do this if the truncate is free and the select is legal.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212640
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Jim Grosbach [Wed, 9 Jul 2014 18:55:52 +0000 (18:55 +0000)]
AArch64: Better codegen for storing to __fp16.
Storing will generally be immediately preceded by rounding from an f32
or f64, so make sure to match those patterns directly to convert into the
FPR16 register class directly rather than going through the integer GPRs.
This also eliminates an extra step in the convert-from-f64 path
which was first converting to f32 and then to f16 from there.
rdar://
17594379
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212638
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