Rafael Espindola [Mon, 2 Apr 2012 22:37:54 +0000 (22:37 +0000)]
Make dominatedBySlowTreeWalk private and assert cases handled by the caller.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153905
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Jakob Stoklund Olesen [Mon, 2 Apr 2012 22:30:39 +0000 (22:30 +0000)]
Allocate virtual registers in ascending order.
This is just the fallback tie-breaker ordering, the main allocation
order is still descending size.
Patch by Shamil Kurmangaleev!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153904
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Pete Cooper [Mon, 2 Apr 2012 22:22:53 +0000 (22:22 +0000)]
Refactored the LiveRangeEdit interface so that MachineFunction, TargetInstrInfo, MachineRegisterInfo, LiveIntervals, and VirtRegMap are all passed into the constructor and stored as members instead of passed in to each method.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153903
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Bill Wendling [Mon, 2 Apr 2012 22:16:50 +0000 (22:16 +0000)]
Add an option to turn off the expensive GVN load PRE part of GVN.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153902
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Owen Anderson [Mon, 2 Apr 2012 22:10:29 +0000 (22:10 +0000)]
Add predicates for checking whether targets have free FNEG and FABS operations, and prevent the DAGCombiner from turning them into bitwise operations if they do.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153901
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Lang Hames [Mon, 2 Apr 2012 19:58:43 +0000 (19:58 +0000)]
During two-address lowering, rescheduling an instruction does not untie
operands. Make TryInstructionTransform return false to reflect this.
Fixes PR11861.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153892
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Rafael Espindola [Mon, 2 Apr 2012 19:44:20 +0000 (19:44 +0000)]
No need to run llvm-as.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153890
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Akira Hatanaka [Mon, 2 Apr 2012 19:25:22 +0000 (19:25 +0000)]
Initial 64 bit direct object support.
This patch allows llvm to recognize that a 64 bit object file is being produced
and that the subsequently generated ELF header has the correct information.
The test case checks for both big and little endian flavors.
Patch by Jack Carter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153889
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Hal Finkel [Mon, 2 Apr 2012 19:09:04 +0000 (19:09 +0000)]
The binutils for the IBM BG/P are too old to support CFI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153886
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Hal Finkel [Mon, 2 Apr 2012 18:31:33 +0000 (18:31 +0000)]
Add triple support for the IBM BG/P and BG/Q supercomputers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153882
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Eric Christopher [Mon, 2 Apr 2012 17:58:52 +0000 (17:58 +0000)]
Turn on the accelerator tables for Darwin.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153880
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Stepan Dyatkovskiy [Mon, 2 Apr 2012 17:16:45 +0000 (17:16 +0000)]
Fast fix for PR12343:
http://llvm.org/bugs/show_bug.cgi?id=12343
We have not trivial way for splitting edges that are goes from indirect branch. We can do it with some tricks, but it should be additionally discussed. And it is still dangerous due to difficulty of indirect branches controlling.
Fix forbids this case for unswitching.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153879
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Roman Divacky [Mon, 2 Apr 2012 15:49:30 +0000 (15:49 +0000)]
Implement the SVR4 byval alignment for aggregates. Fixing a FIXME.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153876
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Silviu Baranga [Mon, 2 Apr 2012 15:46:46 +0000 (15:46 +0000)]
Second part for the 153874 one
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153875
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Silviu Baranga [Mon, 2 Apr 2012 15:20:39 +0000 (15:20 +0000)]
Added fix in TableGen instruction decoder generation. The decoder now breaks for every leaf node.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153874
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Rafael Espindola [Mon, 2 Apr 2012 13:02:57 +0000 (13:02 +0000)]
Add missing 'd'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153872
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Bill Wendling [Mon, 2 Apr 2012 10:01:21 +0000 (10:01 +0000)]
Hack the hack. If we have a situation where an ASM object is defined but isn't
reflected in the LLVM IR (as a declare or something), then treat it like a data
object.
N.B. This isn't 100% correct. The ASM parser should supply more information so
that we know what type of object it is, and what attributes it should have.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153870
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Benjamin Kramer [Mon, 2 Apr 2012 09:13:46 +0000 (09:13 +0000)]
Emit the asm writer's mnemonic table with SequenceToOffsetTable.
This way we can get AVX v-prefixed instructions tail merged with the normal insns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153869
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Benjamin Kramer [Mon, 2 Apr 2012 08:32:38 +0000 (08:32 +0000)]
Move getOpcodeName from the various target InstPrinters into the superclass MCInstPrinter.
All implementations used the same code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153866
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Craig Topper [Mon, 2 Apr 2012 07:48:39 +0000 (07:48 +0000)]
Reorder fields in MatchEntry and OperandMatchEntry to reduce padding. A bit tricky due to the target specific sizes for some of the fields so the ordering is only optimal for the targets in the tree.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153865
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Nadav Rotem [Mon, 2 Apr 2012 07:11:12 +0000 (07:11 +0000)]
Optimizing swizzles of complex shuffles may generate additional complex shuffles.
Do not try to optimize swizzles of shuffles if the source shuffle has more than
a single user, except when the source shuffle is also a swizzle.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153864
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Craig Topper [Mon, 2 Apr 2012 07:01:04 +0000 (07:01 +0000)]
Remove getInstructionName from MCInstPrinter implementations in favor of using the instruction name table from MCInstrInfo. Reduces static data in the InstPrinter implementations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153863
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Eric Christopher [Mon, 2 Apr 2012 06:54:01 +0000 (06:54 +0000)]
Fix CXXFLAGS for huge_val.m4.
Patch by Jeremy Huddleston!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153862
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Craig Topper [Mon, 2 Apr 2012 06:09:36 +0000 (06:09 +0000)]
Make MCInstrInfo available to the MCInstPrinter. This will be used to remove getInstructionName and the static data it contains since the same tables are already in MCInstrInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153860
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Bill Wendling [Mon, 2 Apr 2012 03:33:31 +0000 (03:33 +0000)]
It could come about that we parse the inline ASM before we get a potential
definition for it. In that case, we want to wait for the potential definition
before we create a symbol for it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153859
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Craig Topper [Mon, 2 Apr 2012 00:47:39 +0000 (00:47 +0000)]
Use SequenceToOffsetTable to generate instruction name table for AsmWriter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153857
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Chandler Carruth [Sun, 1 Apr 2012 22:44:09 +0000 (22:44 +0000)]
Start cleaning up the InlineCost class. This switches to sentinel values
rather than a bitfield, a great suggestion by Chris during code review.
There is still quite a bit of cruft in the interface, but that requires
sorting out some awkward uses of the cost inside the actual inliner.
No functionality changed intended here.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153853
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Hal Finkel [Sun, 1 Apr 2012 21:20:14 +0000 (21:20 +0000)]
Fix some 80-col. violations I introduced with the A2 PPC64 core.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153852
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Hal Finkel [Sun, 1 Apr 2012 20:08:17 +0000 (20:08 +0000)]
Enable prefetch generation on PPC64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153851
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Hal Finkel [Sun, 1 Apr 2012 20:08:08 +0000 (20:08 +0000)]
Add LdStSTD* itin. for the PPC64 A2 core.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153850
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Nadav Rotem [Sun, 1 Apr 2012 19:31:22 +0000 (19:31 +0000)]
This commit contains a few changes that had to go in together.
1. Simplify xor/and/or (bitcast(A), bitcast(B)) -> bitcast(op (A,B))
(and also scalar_to_vector).
2. Xor/and/or are indifferent to the swizzle operation (shuffle of one src).
Simplify xor/and/or (shuff(A), shuff(B)) -> shuff(op (A, B))
3. Optimize swizzles of shuffles: shuff(shuff(x, y), undef) -> shuff(x, y).
4. Fix an X86ISelLowering optimization which was very bitcast-sensitive.
Code which was previously compiled to this:
movd (%rsi), %xmm0
movdqa .LCPI0_0(%rip), %xmm2
pshufb %xmm2, %xmm0
movd (%rdi), %xmm1
pshufb %xmm2, %xmm1
pxor %xmm0, %xmm1
pshufb .LCPI0_1(%rip), %xmm1
movd %xmm1, (%rdi)
ret
Now compiles to this:
movl (%rsi), %eax
xorl %eax, (%rdi)
ret
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153848
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Lang Hames [Sun, 1 Apr 2012 19:27:25 +0000 (19:27 +0000)]
Fix typo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153846
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Hal Finkel [Sun, 1 Apr 2012 19:23:08 +0000 (19:23 +0000)]
Set the default PPC node scheduling preference to ILP (for the embedded cores).
The 440 and A2 cores have detailed itineraries, and this allows them to be
fully used to maximize throughput.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153845
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Hal Finkel [Sun, 1 Apr 2012 19:23:04 +0000 (19:23 +0000)]
Add ppc440 itin. entries for LdStSTD*
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153844
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Hal Finkel [Sun, 1 Apr 2012 19:22:57 +0000 (19:22 +0000)]
Use full anti-dep. breaking with post-ra sched. on the embedded ppc cores.
Post-RA scheduling gives a significant performance improvement on
the embedded cores, so turn it on. Using full anti-dep. breaking is
important for FP-intensive blocks, so turn it on (just on the
embedded cores for now; this should also be good on the 970s because
post-ra scheduling is all that we have for now, but that should have
more testing first).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153843
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Hal Finkel [Sun, 1 Apr 2012 19:22:40 +0000 (19:22 +0000)]
Add instruction itinerary for the PPC64 A2 core.
This adds a full itinerary for IBM's PPC64 A2 embedded core. These
cores form the basis for the CPUs in the new IBM BG/Q supercomputer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153842
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Craig Topper [Sun, 1 Apr 2012 18:14:14 +0000 (18:14 +0000)]
Use SequenceToOffsetTable to create instruction name table. Saves space particularly on X86 where AVX instructions just add a 'v' to the front of other instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153841
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Benjamin Kramer [Sun, 1 Apr 2012 14:23:58 +0000 (14:23 +0000)]
Emit the LLVM<->DWARF register mapping as a sorted table and use binary search to do the lookup.
This also avoids emitting the information twice, which led to code bloat. On i386-linux-Release+Asserts
with all targets built this change shaves a whopping 1.3 MB off clang. The number is probably exaggerated
by recent inliner changes but the methods were already enormous with the old inline cost computation.
The DWARF reg -> LLVM reg mapping doesn't seem to have holes in it, so it could be a simple lookup table.
I didn't implement that optimization yet to avoid potentially changing functionality.
There is still some duplication both in tablegen and the generated code that should be cleaned up eventually.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153837
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Chandler Carruth [Sun, 1 Apr 2012 10:41:24 +0000 (10:41 +0000)]
Belatedly address some code review from Chris.
As a side note, I really dislike array_pod_sort... Do we really still
care about any STL implementations that get this so wrong? Does libc++?
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153834
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Chandler Carruth [Sun, 1 Apr 2012 10:36:17 +0000 (10:36 +0000)]
Add some more testing to cover the remaining two cases where
always-inlining is disabled: recursive functions and indirectbr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153833
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Chandler Carruth [Sun, 1 Apr 2012 10:21:05 +0000 (10:21 +0000)]
Fix a pretty scary bug I introduced into the always inliner with
a single missing character. Somehow, this had gone untested. I've added
tests for returns-twice logic specifically with the always-inliner that
would have caught this, and fixed the bug.
Thanks to Matt for the careful review and spotting this!!! =D
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153832
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Chandler Carruth [Sun, 1 Apr 2012 10:11:17 +0000 (10:11 +0000)]
Replace four tiny tests with various uses of grep and not with a single
test and FileCheck.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153831
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Andrew Trick [Sun, 1 Apr 2012 07:24:23 +0000 (07:24 +0000)]
misched: Add finalizeScheduler to complete the target interface.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153827
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Eli Bendersky [Sun, 1 Apr 2012 06:50:01 +0000 (06:50 +0000)]
Removing a file that's no longer being used after the recent refactorings
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153825
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Hal Finkel [Sun, 1 Apr 2012 04:44:16 +0000 (04:44 +0000)]
Split the LdStGeneral PPC itin. class into LdStLoad and LdStStore.
Loads and stores can have different pipeline behavior, especially on
embedded chips. This change allows those differences to be expressed.
Except for the 440 scheduler, there are no functionality changes.
On the 440, the latency adjustment is only by one cycle, and so this
probably does not affect much. Nevertheless, it will make a larger
difference in the future and this removes a FIXME from the 440 itin.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153821
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Rafael Espindola [Sat, 31 Mar 2012 21:54:20 +0000 (21:54 +0000)]
Add a workaround for building with old versions of clang.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153820
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Rafael Espindola [Sat, 31 Mar 2012 18:59:07 +0000 (18:59 +0000)]
Add a triple to the test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153818
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Rafael Espindola [Sat, 31 Mar 2012 18:14:00 +0000 (18:14 +0000)]
Teach CodeGen's version of computeMaskedBits to understand the range metadata.
This is the CodeGen equivalent of r153747. I tested that there is not noticeable
performance difference with any combination of -O0/-O2 /-g when compiling
gcc as a single compilation unit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153817
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Hal Finkel [Sat, 31 Mar 2012 14:45:15 +0000 (14:45 +0000)]
Fix dynamic linking on PPC64.
Dynamic linking on PPC64 has had problems since we had to move the top-down
hazard-detection logic post-ra. For dynamic linking to work there needs to be
a nop placed after every call. It turns out that it is really hard to guarantee
that nothing will be placed in between the call (bl) and the nop during post-ra
scheduling. Previous attempts at fixing this by placing logic inside the
hazard detector only partially worked.
This is now fixed in a different way: call+nop codegen-only instructions. As far
as CodeGen is concerned the pair is now a single instruction and cannot be split.
This solution works much better than previous attempts.
The scoreboard hazard detector is also renamed to be more generic, there is currently
no cpu-specific logic in it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153816
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Chandler Carruth [Sat, 31 Mar 2012 13:18:09 +0000 (13:18 +0000)]
Fix a typo reported in IRC by someone reviewing this code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153815
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Chandler Carruth [Sat, 31 Mar 2012 13:17:18 +0000 (13:17 +0000)]
Give the always-inliner its own custom filter. It shouldn't have to pay
the very high overhead of the complex inline cost analysis when all it
wants to do is detect three patterns which must not be inlined. Comment
the code, clean it up, and leave some hints about possible performance
improvements if this ever shows up on a profile.
Moving this off of the (now more expensive) inline cost analysis is
particularly important because we have to run this inliner even at -O0.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153814
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Chandler Carruth [Sat, 31 Mar 2012 12:48:08 +0000 (12:48 +0000)]
Remove a bunch of empty, dead, and no-op methods from all of these
interfaces. These methods were used in the old inline cost system where
there was a persistent cache that had to be updated, invalidated, and
cleared. We're now doing more direct computations that don't require
this intricate dance. Even if we resume some level of caching, it would
almost certainly have a simpler and more narrow interface than this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153813
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Chandler Carruth [Sat, 31 Mar 2012 12:42:41 +0000 (12:42 +0000)]
Initial commit for the rewrite of the inline cost analysis to operate
on a per-callsite walk of the called function's instructions, in
breadth-first order over the potentially reachable set of basic blocks.
This is a major shift in how inline cost analysis works to improve the
accuracy and rationality of inlining decisions. A brief outline of the
algorithm this moves to:
- Build a simplification mapping based on the callsite arguments to the
function arguments.
- Push the entry block onto a worklist of potentially-live basic blocks.
- Pop the first block off of the *front* of the worklist (for
breadth-first ordering) and walk its instructions using a custom
InstVisitor.
- For each instruction's operands, re-map them based on the
simplification mappings available for the given callsite.
- Compute any simplification possible of the instruction after
re-mapping, and store that back int othe simplification mapping.
- Compute any bonuses, costs, or other impacts of the instruction on the
cost metric.
- When the terminator is reached, replace any conditional value in the
terminator with any simplifications from the mapping we have, and add
any successors which are not proven to be dead from these
simplifications to the worklist.
- Pop the next block off of the front of the worklist, and repeat.
- As soon as the cost of inlining exceeds the threshold for the
callsite, stop analyzing the function in order to bound cost.
The primary goal of this algorithm is to perfectly handle dead code
paths. We do not want any code in trivially dead code paths to impact
inlining decisions. The previous metric was *extremely* flawed here, and
would always subtract the average cost of two successors of
a conditional branch when it was proven to become an unconditional
branch at the callsite. There was no handling of wildly different costs
between the two successors, which would cause inlining when the path
actually taken was too large, and no inlining when the path actually
taken was trivially simple. There was also no handling of the code
*path*, only the immediate successors. These problems vanish completely
now. See the added regression tests for the shiny new features -- we
skip recursive function calls, SROA-killing instructions, and high cost
complex CFG structures when dead at the callsite being analyzed.
Switching to this algorithm required refactoring the inline cost
interface to accept the actual threshold rather than simply returning
a single cost. The resulting interface is pretty bad, and I'm planning
to do lots of interface cleanup after this patch.
Several other refactorings fell out of this, but I've tried to minimize
them for this patch. =/ There is still more cleanup that can be done
here. Please point out anything that you see in review.
I've worked really hard to try to mirror at least the spirit of all of
the previous heuristics in the new model. It's not clear that they are
all correct any more, but I wanted to minimize the change in this single
patch, it's already a bit ridiculous. One heuristic that is *not* yet
mirrored is to allow inlining of functions with a dynamic alloca *if*
the caller has a dynamic alloca. I will add this back, but I think the
most reasonable way requires changes to the inliner itself rather than
just the cost metric, and so I've deferred this for a subsequent patch.
The test case is XFAIL-ed until then.
As mentioned in the review mail, this seems to make Clang run about 1%
to 2% faster in -O0, but makes its binary size grow by just under 4%.
I've looked into the 4% growth, and it can be fixed, but requires
changes to other parts of the inliner.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153812
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Chandler Carruth [Sat, 31 Mar 2012 11:31:24 +0000 (11:31 +0000)]
Add support to the InstVisitor for visiting a generic callsite. The
visitor will now visit a CallInst and an InvokeInst with
instruction-specific visitors, then visit a generic CallSite visitor,
then delegate back to the Instruction visitor and the TerminatorInst
visitors depending on whether a call or an invoke originally. This will
be used in the soon-to-land inline cost rewrite.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153811
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Bill Wendling [Sat, 31 Mar 2012 11:25:18 +0000 (11:25 +0000)]
Move trivial functions into the class definition.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153810
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Bill Wendling [Sat, 31 Mar 2012 11:22:30 +0000 (11:22 +0000)]
Trim headers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153809
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Bill Wendling [Sat, 31 Mar 2012 11:15:43 +0000 (11:15 +0000)]
Indent according to LLVM's style guide.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153808
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Bill Wendling [Sat, 31 Mar 2012 11:10:35 +0000 (11:10 +0000)]
Cleanup whitespace and trim some of the #includes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153807
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Benjamin Kramer [Sat, 31 Mar 2012 11:03:47 +0000 (11:03 +0000)]
Internalize: Remove reference of @llvm.noinline, it was replaced with the noinline attribute a long time ago.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153806
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Bill Wendling [Sat, 31 Mar 2012 10:51:45 +0000 (10:51 +0000)]
These strings aren't 'const char *' but 'char *'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153805
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Bill Wendling [Sat, 31 Mar 2012 10:50:14 +0000 (10:50 +0000)]
Cleanup whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153804
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Bill Wendling [Sat, 31 Mar 2012 10:49:43 +0000 (10:49 +0000)]
Free the codegen options when deleting LTO code generator object.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153803
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Bill Wendling [Sat, 31 Mar 2012 10:44:20 +0000 (10:44 +0000)]
Cleanup whitespace and remove unneeded 'extern' keyword on function definitions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153802
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Chandler Carruth [Sat, 31 Mar 2012 10:38:48 +0000 (10:38 +0000)]
Clean up the naming in this test. Someone pointed this out in review at
one point, and I forgot to go back and clean it up. Sorry about that. =/
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153801
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Chandler Carruth [Sat, 31 Mar 2012 09:22:33 +0000 (09:22 +0000)]
FileCheck-ize this test, and generally tidy it up prior to changing
things around.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153799
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Duncan Sands [Sat, 31 Mar 2012 08:20:11 +0000 (08:20 +0000)]
I noticed in passing that the Metadata getIfExists method was creating a new
node and returning it if one didn't exist.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153798
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Hal Finkel [Sat, 31 Mar 2012 03:38:40 +0000 (03:38 +0000)]
Correctly vectorize powi.
The powi intrinsic requires special handling because it always takes a single
integer power regardless of the result type. As a result, we can vectorize
only if the powers are equal. Fixes PR12364.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153797
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Andrew Trick [Sat, 31 Mar 2012 02:39:17 +0000 (02:39 +0000)]
comment typo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153796
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Akira Hatanaka [Sat, 31 Mar 2012 02:38:36 +0000 (02:38 +0000)]
Select static relocation model if it is jitting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153795
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Andrew Trick [Sat, 31 Mar 2012 01:35:59 +0000 (01:35 +0000)]
Introduce Register Units: Give each leaf register a number.
First small step toward modeling multi-register multi-pressure. In the
future, register units can also be used to model liveness and
aliasing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153794
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Jakob Stoklund Olesen [Sat, 31 Mar 2012 00:06:44 +0000 (00:06 +0000)]
Add a 2 byte safety margin in offset computations.
ARMConstantIslandPass still has bugs where jump table compression can
cause constant pool entries to go out of range.
Add a safety margin of 2 bytes when placing constant islands, but use
the real max displacement for verification.
<rdar://problem/
11156595>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153789
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Jakob Stoklund Olesen [Sat, 31 Mar 2012 00:06:42 +0000 (00:06 +0000)]
Add more debugging output to ARMConstantIslandPass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153788
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Bill Wendling [Fri, 30 Mar 2012 23:26:06 +0000 (23:26 +0000)]
* Set the scope attributes for the ASM symbol we added to be the value passed
into the function.
* Reorder some header files.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153783
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Benjamin Kramer [Fri, 30 Mar 2012 23:13:40 +0000 (23:13 +0000)]
Rip out emission of the regIsInRegClass function for the asm printer.
It's slow, bloated and completely redundant with MCRegisterClass::contains.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153782
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Jim Grosbach [Fri, 30 Mar 2012 21:54:22 +0000 (21:54 +0000)]
ARM fix encoding fixup resolution for ldrd and friends.
The 8-bit payload is not contiguous in the opcode. Move the upper nibble
over 4 bits into the correct place.
rdar://
11158641
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153780
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Jakob Stoklund Olesen [Fri, 30 Mar 2012 21:12:52 +0000 (21:12 +0000)]
Use SequenceToOffsetTable in emitRegisterNameString.
This allows suffix sharing in register names. (AX is a suffix of EAX).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153777
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Jakob Stoklund Olesen [Fri, 30 Mar 2012 20:24:14 +0000 (20:24 +0000)]
Reapply 153764 and 153761 with a fix.
Use an explicit comparator instead of the default.
The sets are sorted, but not using the default comparator. Hopefully,
this will unbreak the Linux builders.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153772
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Rafael Espindola [Fri, 30 Mar 2012 20:09:06 +0000 (20:09 +0000)]
Revert 153764 and 153761. They broke a --enable-optimized --enable-assertions
--enable-expensive-checks build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153771
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Jim Grosbach [Fri, 30 Mar 2012 19:59:02 +0000 (19:59 +0000)]
ARM assembler should prefer non-aliases encoding of cmp.
When an immediate is both a value [t2_]so_imm and a [t2_]so_imm_neg,
we want to use the non-negated form to make sure we prefer the normal
encoding, not the aliased encoding via the negation of, e.g., 'cmp.w'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153770
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Jim Grosbach [Fri, 30 Mar 2012 18:53:01 +0000 (18:53 +0000)]
ARM encoding for VSWP got the second operand incorrect.
Make the non-tied register operand names line up with what the base
class encoding handler expects.
rdar://
11157236
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153766
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Jim Grosbach [Fri, 30 Mar 2012 18:39:43 +0000 (18:39 +0000)]
ARM can only use narrow encoding for low regs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153765
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Jakob Stoklund Olesen [Fri, 30 Mar 2012 17:42:04 +0000 (17:42 +0000)]
Compress SimpleValueType lists by sharing.
Many register classes have the same value types. Share the table space.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153764
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Jakob Stoklund Olesen [Fri, 30 Mar 2012 17:25:43 +0000 (17:25 +0000)]
Compress register lists by sharing suffixes.
TableGen emits lists of sub-registers, super-registers, and overlaps. Put
them all in a single table and use a SequenceToOffsetTable to share
suffixes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153761
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Jakob Stoklund Olesen [Fri, 30 Mar 2012 17:25:40 +0000 (17:25 +0000)]
Add a SequenceToOffsetTable to TableGen.
This is similar to the StringToOffsetTable we use to produce string
tables, but it can be used for other sequences than strings, and it
eliminates entries for suffixes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153760
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Jim Grosbach [Fri, 30 Mar 2012 17:20:40 +0000 (17:20 +0000)]
ARM integrated assembler should encoding choice for add/sub imm.
For 'adds r2, r2, #56' outside of an IT block, the 16-bit encoding T2
can be used for this syntax. Prefer the narrow encoding when possible.
rdar://
11156277
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153759
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Rafael Espindola [Fri, 30 Mar 2012 16:46:21 +0000 (16:46 +0000)]
Handle unreachable code in the dominates functions. This changes users when
needed for correctness, but still doesn't clean up code that now unnecessary
checks for reachability.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153755
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Danil Malyshev [Fri, 30 Mar 2012 16:45:19 +0000 (16:45 +0000)]
Re-factored RuntimeDyLd:
1. The main works will made in the RuntimeDyLdImpl with uses the ObjectFile class. RuntimeDyLdMachO and RuntimeDyLdELF now only parses relocations and resolve it. This is allows to make improvements of the RuntimeDyLd more easily. In addition the support for COFF can be easily added.
2. Added ARM relocations to RuntimeDyLdELF.
3. Added support for stub functions for the ARM, allowing to do a long branch.
4. Added support for external functions that are not loaded from the object files, but can be loaded from external libraries. Now MCJIT can correctly execute the code containing the printf, putc, and etc.
5. The sections emitted instead functions, thanks Jim Grosbach. MemoryManager.startFunctionBody() and MemoryManager.endFunctionBody() have been removed.
6. MCJITMemoryManager.allocateDataSection() and MCJITMemoryManager. allocateCodeSection() used JMM->allocateSpace() instead of JMM->allocateCodeSection() and JMM->allocateDataSection(), because I got an error: "Cannot allocate an allocated block!" with object file contains more than one code or data sections.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153754
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Jim Grosbach [Fri, 30 Mar 2012 16:31:31 +0000 (16:31 +0000)]
ARM assembly parsing needs to be paranoid about negative immediates.
Make sure to treat immediates as unsigned when doing relative comparisons.
rdar://
11153621
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153753
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Rafael Espindola [Fri, 30 Mar 2012 15:52:11 +0000 (15:52 +0000)]
Add computeMaskedBitsLoad back, as it was the change to instsimplify that
caused the slowdown last time.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153747
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Benjamin Kramer [Fri, 30 Mar 2012 13:02:58 +0000 (13:02 +0000)]
Add a note about a missed cmov -> sbb opportunity.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153741
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Bill Wendling [Fri, 30 Mar 2012 10:29:38 +0000 (10:29 +0000)]
Cleanup whitespace. Doxygenize comments. And indent to llvm coding standards.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153740
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James Molloy [Fri, 30 Mar 2012 09:15:32 +0000 (09:15 +0000)]
Ensure conditional BL instructions for ARM are given the fixup fixup_arm_condbranch.
Patch by Tim Northover!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153737
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Evan Cheng [Fri, 30 Mar 2012 01:24:39 +0000 (01:24 +0000)]
ARM target should allow codegenprep to duplicate ret instructions to enable tailcall opt. rdar://
11140249
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153717
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Bill Wendling [Fri, 30 Mar 2012 00:26:54 +0000 (00:26 +0000)]
Testcase for r153710.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153711
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Bill Wendling [Fri, 30 Mar 2012 00:05:02 +0000 (00:05 +0000)]
Add testcase for r153705
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153706
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Bill Wendling [Fri, 30 Mar 2012 00:02:55 +0000 (00:02 +0000)]
If we have a VLA that has a "use" in a metadata node that's then used
here but it has no other uses, then we have a problem. E.g.,
int foo (const int *x) {
char a[*x];
return 0;
}
If we assign 'a' a vreg and fast isel later on has to use the selection
DAG isel, it will want to copy the value to the vreg. However, there are
no uses, which goes counter to what selection DAG isel expects.
<rdar://problem/
11134152>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153705
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Lang Hames [Thu, 29 Mar 2012 23:52:38 +0000 (23:52 +0000)]
Change the constant in this testcase so that it results in a constant pool
load.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153704
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Bill Wendling [Thu, 29 Mar 2012 23:23:59 +0000 (23:23 +0000)]
Revert r153694. It was causing failures in the buildbots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153701
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Jakob Stoklund Olesen [Thu, 29 Mar 2012 23:14:26 +0000 (23:14 +0000)]
Invalidate liveness in ARMConstantIslandPass.
This pass splits basic blocks to insert constant islands, and it
doesn't recompute the live-in lists. No later passes depend on accurate
liveness information.
This fixes PR12410 where the machine code verifier was complaining.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153700
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Jakob Stoklund Olesen [Thu, 29 Mar 2012 22:54:32 +0000 (22:54 +0000)]
Prefer even-odd D-register pairs.
We are sometimes allocatinog from the DPair register class which
contains odd-even pairs in addition to the Q registers.
Place the Q registers first in the DPair allocation order as they can be
copied with a single instruction. The odd-even pairs should only be
allocated as a last resort.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153699
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