pinctrl: rockchip: Add rk3288 GPIO0_D0 ~ GPIO0_D7 pins support

Change-Id: If8b51cc98ea38076b4721b09a307299ac5feed0f
Signed-off-by: David Wu <david.wu@rock-chips.com>

CHROMIUM: arm64: dts: rockchip: add warm reset quirk for rk3399 dwc3

This patch adds warm reset on resume quirk for rk3399 platform.

BUG=chrome-os-partner:58347
TEST=Plug an USB3 flash drive in rk3399 Kevin board Type-C
port, then set system enter S3. Wakeup system, check if USB3
device can be detected after resume.

Change-Id: I5d3273e9603da01395fa7cd2e2becfe350faed1d
Signed-off-by: William wu <wulf@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/412489
Commit-Ready: Guenter Roeck <groeck@chromium.org>
Tested-by: Guenter Roeck <groeck@chromium.org>
Tested-by: Inno Park <ih.yoo.park@samsung.com>
Reviewed-by: Guenter Roeck <groeck@chromium.org>
Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com>

CHROMIUM: usb: dwc3: add usb3_warm_reset_on_resume_quirk

This patch add a quirk for some special platforms (e.g. rk3399
platform) which need to do warm reset for USB3 device on resume.

BUG=chrome-os-partner:58347
TEST=Plug an USB3 flash drive in rk3399 Kevin board Type-C
port, then set system enter S3. Wakeup system, check if USB3
device can be detected after resume.

Change-Id: I19acc0560001481e5a952175433e82d17dfb3a40
Signed-off-by: William wu <wulf@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/412488
Commit-Ready: Guenter Roeck <groeck@chromium.org>
Tested-by: Guenter Roeck <groeck@chromium.org>
Tested-by: Inno Park <ih.yoo.park@samsung.com>
Reviewed-by: Guenter Roeck <groeck@chromium.org>
Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com>

CHROMIUM: xhci: fix USB3 device undetected after resume

Some xHC controllers (e.g. Rockchip rk3399) integrated in
DWC3 IP, will be powered down in S3, and reinitialized after
resume.

However, if a USB3 device is plugged before system enter S3,
the device will be disconnected after resume because of xHC
lose power. And the device can't be detected again even if
we reinitialize xHC. In this case, CCS and CSC is '0' and
can't reflect the current state of the port, also the link
state stays in Rx.Detect.

So try to do warm reset on resume to reset USB3 device to
the default state, also reset a USB3 link, and re-exchange
link configuration information.

BUG=chrome-os-partner:58347
TEST=Plug an USB3 flash drive in rk3399 Kevin board Type-C
port, then set system enter S3. Wakeup system, check if USB3
device can be detected after resume.

Change-Id: I90975a48866569f2c2422a244afc618a3e427f57
Signed-off-by: William wu <wulf@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/412487
Commit-Ready: Guenter Roeck <groeck@chromium.org>
Tested-by: Guenter Roeck <groeck@chromium.org>
Tested-by: Inno Park <ih.yoo.park@samsung.com>
Reviewed-by: Guenter Roeck <groeck@chromium.org>
Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com>

arm64: dts: rk3399: sapphire-excavator: enabled pcie

Change-Id: I762ef100bf31142b4ebb359594be9c8e16cd4fc7
Signed-off-by: Wu Liangqing <wlq@rock-chips.com>

drm: bridge: dw-hdmi: unregister the hpd workqueue when unbind

Change-Id: Ib692a4e42843a6a9c89c5a92f79a7dd85a4ae534
Signed-off-by: algea.cao <algea.cao@rock-chips.com>

video/rockchip: rga2: fix rga timeout when do scaling

rk3368 rga sometime may timeout when do scaling, and it can't
be restore until do a non-scale rga work.

So hack that, if timeout with scaling work, do a tiny non-scale rga
work before normal work.

Change-Id: I4598741347c44a1ff3c2272270f4c6a1def36177
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>

arm64: dts: rockchip: sapphire-excavator: enabled hdmiin

Change-Id: I5d09ee8e07e515270fadfcdb1e8bbb98cbfaa8ac
Signed-off-by: Wu Liangqing <wlq@rock-chips.com>

ARM64: rockchip_defconfig: default to enable optee driver

Change-Id: I8aa0610074960e70fd0b9e5c046960a1038ed665
Signed-off-by: Zhang Zhijie <zhangzj@rock-chips.com>

ARM: rockchip_defconfig: default to enable optee driver

Change-Id: I9364ddb9e7f05a20d5e283b9386b98b10d9c5552
Signed-off-by: Zhang Zhijie <zhangzj@rock-chips.com>

OP-TEE: fix operate user pointer bug in optee driver

Fix operate user pointer bug which causes panic in kernel.

Change-Id: I7fcf74fb68dd0959e5ba64635c614f954d065281
Signed-off-by: Zhang Zhijie <zhangzj@rock-chips.com>

UPSTREAM: regulator: fan53555: Add support for FAN53555UC13X type

IC type options 00, 13 and 23 are sharing the same DIE_ID 0.
Let's differentiate between these revisions.
FAN53555UC13X has the ID 0 and REV 0xf, starts at 800mV and
increments in 10mV steps.

Change-Id: I3fdcd305013ccef73145da2b84f303021304876a
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Signed-off-by: Mark Brown <broonie@kernel.org>
(cherry picked from commit e57cbb70b7b3773f78fc6b8b70ab1eb3367e5350)
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>

UPSTREAM: regulator: fan53555: Add support for FAN53555BUC18X type

FAN53555BUC18X has the DIE_ID 8, starts at 600mV and
increments in 10mV steps.

Change-Id: If4f7d2d911748c42e79ad8268b884275d4230aef
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Signed-off-by: Mark Brown <broonie@kernel.org>
(cherry picked from commit 5e39cf49729b910795daa0b86052463d23c0a18d)
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>

UPSTREAM: ARM: dts: rockchip: fix MIPI interrupt on rk3288

This isn't currently used by the driver but the correct value is 19
since DSIHOST0 is 51 in the TRM and the GIC offset requires 32 to be
subtracted.

Change-Id: I81ad5143296227aa0cd67f7d33e23db6ecc6cf35
Signed-off-by: John Keeping <john@metanate.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from commit 5415ba40650900f7d663a4b79f346c45dddd4ce0)
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>

FROMLIST: regulator: rk808: Fix RK818 LDO2

Set the correct voltage select register for LDO2.

(am from https://patchwork.kernel.org/patch/9639275/)
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Change-Id: I877d482e937920cdb3bf820a7c2cf7c650b24eff
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>

arm: dts: rk3288-evb: fix panel black when uboot switch to kernel

Change-Id: Id2d42aa54788148ad8eb4ddb8d0755c9831d9997
Signed-off-by: xubilv <xbl@rock-chips.com>

arm: dts: rk3288-evb: fix the edp timing node is not recognized bug

Change-Id: I1f1ef41cf18a2be41763c1c711c5440750cfe314
Signed-off-by: xubilv <xbl@rock-chips.com>

arm: dts: rk3288-android: support uboot-logo and kernel-logo display

Change-Id: Id409b724ae408ad11149ea74c3fad9c06b7e177d
Signed-off-by: xubilv <xbl@rock-chips.com>

arm: dts: rk3288: delete DCLK in cru assigned-clocks

Change-Id: Ie608fb96ca591654d63cbfbd5e671198ca39157c
Signed-off-by: xubilv <xbl@rock-chips.com>

arm: dts: rk3288-android: reserve memory for drm-logo

Change-Id: I43fb85dd5aa4eb5c49a2e0953a1c90fa1a6cba96
Signed-off-by: xubilv <xbl@rock-chips.com>

arm: dts: rk3288-evb: resolve conflict between edp_panel and mipi_panel

if edp_panel add disp_timings, it will conflict with mipi_panel.

Change-Id: Ic6d9bcb5f38670d203ca9c220354f1ac476ccbfb
Signed-off-by: xubilv <xbl@rock-chips.com>

UPSTREAM: ARM: DTS: Fix register map for virt-capable GIC

Since everybody copied my own mistake from the DT binding example,
let's address all the offenders in one swift go.

Most of them got the CPU interface size wrong (4kB, while it should
be 8kB), except for both keystone platforms which got the control
interface wrong (4kB instead of 8kB).

In a few cases where I knew for sure what implementation was used,
I've added the "arm,gic-400" compatible string. I'm 99% sure that
this is what everyone is using, but short of having the TRM for
all the other SoCs, I've left them alone.

Change-Id: I15f66453fa9db952d1758cd5b61432405b019dc8
Acked-by: Shawn Guo <shawnguo@kernel.org>
Acked-by: Tony Lindgren <tony@atomide.com>
Acked-by: Santosh Shilimkar <ssantosh@kernel.org>
Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Matthias Brugger <matthias.bgg@gmail.com>
Acked-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
(cherry picked from commit 387720c93812f1e702c20c667cb003a356e24a6c)
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>

ARM: dts: rk3288: correct some errors

Change-Id: Ic5cd80fd32ffa02846a70d8e756a2b8285b512f3
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>

ARM: rockchip_defconfig: enable camsys driver

Change-Id: Ibd02e0fa03a8193435dcb0e1a2b238938c27892e
Signed-off-by: xcq <shawn.xu@rock-chips.com>

ASoC: codecs: cleanup codes

Change-Id: I42d9d6c24fc879b422fd9f18fe3af7d6f3b26d90
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>

ASoC: rockchip: cleanup codes

Change-Id: Ieacbcc8311fa683394c57a21c69099620b294ffc
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>

ARM: dts: rockchip: enable isp for rk3288 evb

Change-Id: I2291f43ec9e3b7e3cf5a306f9bfcfd60083be3c3
Signed-off-by: xcq <shawn.xu@rock-chips.com>

camera: rockchip: camsys v0.0x21.0xc

camsys driver support rk3288

Change-Id: Iddcca33b40df58c75164bdc8828ac0b82c2c6ff6
Signed-off-by: xcq <shawn.xu@rock-chips.com>

arm: dts: rk3288: add isp config

Change-Id: I00883343c8addff1adc71bef5001d3064b829d97
Signed-off-by: xcq <shawn.xu@rock-chips.com>

drm/rockchip: rga: fix smatch check

Change-Id: I884ca0d65f1092720262ee96c85803071cbc6284
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>

drm/rockchip: rga: add buf flush flag

The buffer have been accessed by CPU needs to be synced
for the device to see the most up-to-date.

So introduce a flag here to see if a buffer need flush cache.

Change-Id: I68457aa528d04acc6f92dfa2171d8c807ab657a6
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>

arm64: dts: rockchip: add linestate check dis quirk for rk3328 dwc3

rk3328 dwc3 has a problem that USB 2.0 MAC lineState not
reflect the expected line state (J) during transmission.
Add this quirk to add the ipgap between (tkn to tkn/data)
with 40 bit times of TXENDDELAY, and linestate is ignored
during this 40 bit times delay.

Change-Id: I76895476bff94c2198a5d8df7e73b9d54fbb96ed
Signed-off-by: William Wu <william.wu@rock-chips.com>

arm64: dts: rockchip: add linestate check dis quirk for rk3399 dwc3

rk3399 dwc3 has a problem that USB 2.0 MAC lineState not
reflect the expected line state (J) during transmission.
Add this quirk to add the ipgap between (tkn to tkn/data)
with 40 bit times of TXENDDELAY, and linestate is ignored
during this 40 bit times delay.

Change-Id: Ife9d46dbf2a8d4a8faa2fc20bfad442d6bb88a05
Signed-off-by: William Wu <william.wu@rock-chips.com>

FROMLIST: usb: dwc3: add disable u2mac linestate check quirk

This patch adds a quirk to disable USB 2.0 MAC linestate check
during HS transmit. Refer the dwc3 databook, we can use it for
some special platforms if the linestate not reflect the expected
line state(J) during transmission.

When use this quirk, the controller implements a fixed 40-bit
TxEndDelay after the packet is given on UTMI and ignores the
linestate during the transmit of a token (during token-to-token
and token-to-data IPGAP).

On some rockchip platforms (e.g. rk3399), it requires to disable
the u2mac linestate check to decrease the SSPLIT token to SETUP
token inter-packet delay from 566ns to 466ns, and fix the issue
that FS/LS devices not recognized if inserted through USB 3.0 HUB.

(am from https://patchwork.kernel.org/patch/9684951/)
Change-Id: I6298f59a5b89a76a90c628a58c932942ede2c3ef
Signed-off-by: William Wu <william.wu@rock-chips.com>

UPSTREAM: usb: dwc3: Add support for device L1 exit

For the usb31 IP and from version 2.90a of the usb3 IP, the core
supports HW exit from L1 in HS. Enable it, otherwise the controller may
never exit from LPM to do a transfer.

Conflicts:
drivers/usb/dwc3/core.c
drivers/usb/dwc3/core.h

Change-Id: I074d3ab2e386b872800e2c9898398d3696228527
Signed-off-by: John Youn <johnyoun@synopsys.com>
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
Signed-off-by: William Wu <wulf@rock-chips.com>
(cherry picked from commit 0bb39ca1ad8758f109cd2e7b30a5316f3097346a)

cpufreq: dt: support checking initial rate

Bootloader or kernel sets CPU frequency to an initial value before cpufreq
starts on rockchip platform, if cpu's opp table is modified to a specified
value, it will cause an issue.

For example, the initial frequency is 816MHz and voltage set by hardware
is 900mV:
1. there is only one opp whose frequency is 816MHz and voltage is 850mV
in opp table list, as they frequency is equal, the voltage will not be
changed, it is still 900mV and a little too large relative to 850mV.
2. there is only one opp whose frequency is 1200MHz and voltage is 1100mV
in opp table list, as it doesn't set voltage to 1100mV before set frequency
to 1200MHz in the dev_pm_opp_set_rate function, the initial voltage 900mV
cann't supply for 1200MHz, the system crash.

Change-Id: Iba41536367ba5802dd8f7f37e245f0e5781eb643
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>

arm64: dts: rockchip: delete cpu-avs device node

Change-Id: I86dd02761a4156768af018c0c90a61afb0ff74a6
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>

PM / AVS: rockchip-cpu-avs: remove driver

The CPUFREQ_CREATE_POLICY and CPUFREQ_START had removed on 'master'
of git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git.
So the driver will be unused in the future.

Change-Id: I7e26a8050c4745d3390302babeafbbc40ff5e707
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>

PM / OPP: remove check of supported_hw and prop_name when remove opp table

It's also removed in
commit fa30184d192e ("PM / OPP: Return opp_table from dev_pm_opp_set_*()
routines").

This path fixes the below errors:
rk3368:/ # echo 0 > /sys/devices/system/cpu/cpu7/online
[   39.475170] CPU7: shutdown
[   39.478565] psci: CPU7 killed.
rk3368:/ # echo 0 > /sys/devices/system/cpu/cpu6/online
[   39.541350] CPU6: shutdown
[   39.544308] psci: CPU6 killed.
rk3368:/ # echo 0 > /sys/devices/system/cpu/cpu5/online
[   39.601355] CPU5: shutdown
[   39.604446] psci: CPU5 killed.
rk3368:/ # echo 0 > /sys/devices/system/cpu/cpu4/online
[   40.148213] CPU4: shutdown
[   40.151526] psci: CPU4 killed.
rk3368:/ # echo 1 > /sys/devices/system/cpu/cpu4/online
[   44.915743] Detected VIPT I-cache on CPU4
[   44.915997] CPU4: update cpu_capacity 1024
[   44.916031] CPU4: Booted secondary processor [410fd033]
[   44.921409] cpu cpu4: dev_pm_opp_set_prop_name: Already have prop-name L1
[   44.921554] cpu cpu4: Failed to set prop name
[   44.921597] cpu cpu4: Failed to set_opp_info
[   44.923002] cpu cpu4: opp_list_debug_create_link: Failed to create link
[   44.923061] cpu cpu4: _add_opp_dev: Failed to register opp debugfs (-12)

Change-Id: I4143a8f0327964244dc63864ba159f306890fb16
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>

arm64: dts: rk3368: add opp-microvolt-L0/1 property for cpu opp table

Change-Id: Ib21738447057648a24f2e66b637de280bb2b82eb
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>

arm64: dts: rk3368: add leakage-voltage-sel property for cpu opp table

Change-Id: I5f72c3cd59216723018a021b77081f9fbd630b0e
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>

cpufreq: rockchip: Provide runtime initialised driver

This path introduces a rockchip-cpufreq driver, which can determine
available OPPs and select a suitable voltage for available OPPs
according to SoC version and leakage valuses in eFuse at runtime.

If all cpus of a cluster are downed, opp table will be removed,
prop-name and supported_hw are noneffective. So add a hotcpu notifier
to set them again when a cpu of the closed cluster is upped.

Change-Id: I43ab3e2cad4a9fefd5be5b0596cd841c392d7a8b
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>

Documentation: dt: add bindings for rockchip-cpufreq

Add the device tree bindings document for ROCKCHIP CPUFreq driver.
The operating-points-v2 binding allows us to provide an opp-supported-hw
property for each OPP to define when it is available and an
opp-microvolt-<name> property to choose a suitable voltage for OPP.

This driver reads SoC version and leakage values from eFuse and
provides them as matching data to the opp framework.

Change-Id: I10f959edd46668bedf3be4835bb5ec63e089808d
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>

ARM64: dts: rk3368-android: enabled mailbox/mailbox_scpi

Change-Id: I664f6d928ec86990222de64baf0f50ab2f8584da
Signed-off-by: Wu Liangqing <wlq@rock-chips.com>

ARM64: dts: rk3368-p9: set vccio_wl to 1.8v

Change-Id: I8683049b689f97af8ff36948db6ce7887b308a85
Signed-off-by: Wu Liangqing <wlq@rock-chips.com>

phy: rockchip-inno-usb2: tuning USB 2.0 PHY when resume

The USB 2.0 PHY may lose tuning config after resume if the
PD turn off its power when suspend. So we need to tune USB
2.0 PHY again when resume.

Change-Id: Ib34de165ccd7d22598e77e5ac0fed1233e7adba0
Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com>

drm/rockchip: logo: fix logo memory end on free

It's mistake using logo size as logo memory end, and that would cause:

[    8.443899] BUG: Bad page state in process recovery  pfn:7dcc3
[    8.443903] page:effb3860 count:0 mapcount:3 mapping:eebdf784 index:0x15
[    8.443907] flags: 0x4004007c(referenced|uptodate|dirty|lru|active|swapbacked)
[    8.443918] page dumped because: PAGE_FLAGS_CHECK_AT_FREE flag(s) set
[    8.443922] bad because of flags:
[    8.443924] flags: 0x60(lru|active)
[    8.443930] Modules linked in:
[    8.443935] CPU: 0 PID: 170 Comm: recovery Tainted: G    B           4.4.55 #70
[    8.443939] Hardware name: Rockchip (Device Tree)
[    8.443947] [<c010f55c>] (unwind_backtrace) from [<c010b7ec>] (show_stack+0x10/0x14)
[    8.443955] [<c010b7ec>] (show_stack) from [<c03bc3a8>] (dump_stack+0x7c/0x9c)
[    8.443963] [<c03bc3a8>] (dump_stack) from [<c01eb430>] (bad_page+0xe4/0x114)
[    8.443971] [<c01eb430>] (bad_page) from [<c01eb550>] (free_pages_prepare+0xf0/0x294)
[    8.443978] [<c01eb550>] (free_pages_prepare) from [<c01ed654>] (free_hot_cold_page+0x28/0x14c)
[    8.443987] [<c01ed654>] (free_hot_cold_page) from [<c01ed954>] (free_reserved_area+0x90/0xdc)
[    8.443996] [<c01ed954>] (free_reserved_area) from [<c04749f4>] (rockchip_free_loader_memory+0xf0/0x118)
[    8.444006] [<c04749f4>] (rockchip_free_loader_memory) from [<c0475b14>] (rockchip_drm_fb_destroy+0xbc/0xd0)
[    8.444015] [<c0475b14>] (rockchip_drm_fb_destroy) from [<c04581e0>] (drm_mode_set_config_internal+0xa8/0xc4)
[    8.444024] [<c04581e0>] (drm_mode_set_config_internal) from [<c045ce24>] (drm_mode_setcrtc+0x3a8/0x464)
[    8.444032] [<c045ce24>] (drm_mode_setcrtc) from [<c044f634>] (drm_ioctl+0x278/0x43c)
[    8.444039] [<c044f634>] (drm_ioctl) from [<c023ea58>] (do_vfs_ioctl+0x564/0x6a0)
[    8.444047] [<c023ea58>] (do_vfs_ioctl) from [<c023ebe0>] (SyS_ioctl+0x4c/0x74)
[    8.444055] [<c023ebe0>] (SyS_ioctl) from [<c0107180>] (ret_fast_syscall+0x0/0x3c

Change-Id: I833a27464d9d33f6864039faa61e7500a3b936b3
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>

clk: rockchip: rk3288: fix up the hclk_vio register

fix up the hclk_vio register order,
before setting clk critical.

Change-Id: Ia3a4d2fcb8ee8164dfe621d2d081076000a30937
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

arm: dts: rk3288-evb: remove limit usage for vopb

There are many notes - Don't use vopb for HDMI, save it for eDP,
let's remove them for kinds of products.

Change-Id: Id8ef9ec8ac853e7b68527f59a9a8870b5a45d8f2
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>

phy: rockchip-inno-usb2: tuning USB 2.0 squelch detection threshold

According to USB 2.0 Spec Table 7-7, the High-speed squelch
detection threshold Min 100mV and Max 150mV, and we set USB
2.0 PHY0 and PHY1 squelch detection threshold to 150mV by
default, so if the amplitude of differential voltage envelope
is < 150 mV, the USB 2.0 PHYs envelope detector will indicate
it as squelch.

On RK3399 box, if we connect usb device with a 4 meter cable,
we can see that the impedance of U2 cable is too big according
to the eye-diagram test report, and this cause serious signal
attenuation at the end of receiver, the amplitude of differential
voltage falls below 150mV.

This patch aims to reduce the PHY0 and PHY1 otg-ports squelch
detection threshold to 125mV (host-ports still use 150mV by
default), this is helpful to increase USB 2.0 PHY compatibility.

Change-Id: Iec8b4043a3440d6f2a5fb18ff59ac0f4988019e9
Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com>

video: rockchip: rk322x_lcdc: fix error condition

Change-Id: I1c28a815beb74a7566886aef666454ec1513970b
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>

drm/rockchip: fix hdmi no display when resume or switch resolution

spelling mistake cause hdmi phy configure error, now correct it

Change-Id: I548d76dd44e8d39e35b95138ec3d25b358cf3376
Signed-off-by: xuhuicong <xhc@rock-chips.com>

ARM64: configs: rockchip_linux: enable rk3328 internal codec

Change-Id: I03ad95e771a4b506d6462be5dade0553eb121fcc
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>

ARM64: dts: rk3328-evb: add spdif sound

Change-Id: I76adc6286d831f513da3f5547975d7fcd3c392e9
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>

ARM64: configs: rockchip: enable rk3328 internal codec

Change-Id: I7c71d81e768fcd58b935f9f40d71c5834d04573d
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>

ARM64: dts: rk3328-evb: add support for internal codec sound

Change-Id: I8b1705f592d42e2f1d351ce5a7880993f7757b94
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>

ARM64: dts: rk3328: add acodec node

Change-Id: I5d564066fa1d399c2c4fabf753eb6f698136a52c
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>

ASoC: codecs: add support for rk3328

Change-Id: I66ff61c18fe70135fd7ac0569954263743263a3a
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>

drm/panel: Change dlen from u16 to u8

U8_MAX payload length can meet most requirements

Change-Id: I77e5780bde72b4229ab36d961dc7498f7c78a468
Signed-off-by: WeiYong Bi <bivvy.bi@rock-chips.com>

drm/bridge: analogix: fix edid not works

Change-Id: I1a964b51d0d137e66ad5d073a2eef2fb22770bba
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>

ARM: rockchip_defconfig: enable DEVFREQ_GOV_SIMPLE_ONDEMAND

Change-Id: I3cdcceca0f5c743b84ab1ec159bb576a7a5ab5a5
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>

ARM: rockchip_defconfig: update by savedefconfig

Change-Id: I4b5ec60a8beeb014754855a4865bc7fc26f2fddd
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>

drm/panel: support transmit DSI packet

Change-Id: I6115479eebc05b44a8c01cd72919db0e5a6cb1f9
Signed-off-by: WeiYong Bi <bivvy.bi@rock-chips.com>

phy: rockchip-inno-mipi-dphy: Add fixed timing param table

Change-Id: Ia6a92833f4b597ac5f9af694644714a7b71b3375
Signed-off-by: WeiYong Bi <bivvy.bi@rock-chips.com>

ASoC: rockchip: add rt5651_tc358749x driver

add rockchip_rt5651_tc358749x machine driver to
support HDMIIn function

Change-Id: Ieb0e046bec60ea0a27ee49ce1204b032ad646724
Signed-off-by: LuoXiaoTan <lxt@rock-chips.com>

ASoC: codecs: add tc358749x codec driver

add tc358749x codec driver for hdmiin function

Change-Id: I819ac80ced59b5d81d547f7ba2c7ebc7bee7f845
Signed-off-by: LuoXiaoTan <lxt@rock-chips.com>

arm: dts: rk3288-evb-rk818: set tsadc default pinctrl to gpio

When rockchip,hw-tshut-mode is 0, means that tshut mode is CRU,
then the pinctrl should default to be GPIO.

If the tshut mode is GPIO, then the pinctrl should default to be
OTP_OUT.

Change-Id: Ic6e53a96823baf4671f9bad261ed34586512634f
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>

arm: dts: rk3288-android: set PWM_POLARITY_INVERTED to 0

Change-Id: I47623781f93f2f325f76e1fa4a7ffe515623064e
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>

usb: dwc_otg_310: support vbus controlled by both gpio and pmic

On some rockchip platforms (e.g. rk3368), usb vbus 5v is controlled
by both gpio and pmic at the same time. So we need to set gpio and
pmic when enable/disable usb vbus power.

Change-Id: I327a87f16662026eaab1b6577d0b0116c4b2671f
Signed-off-by: William Wu <wulf@rock-chips.com>

arm64: dts: rk3368: fix string error for sdio

Change-Id: Ia7a122bd52d71442c31f71677ae24c52c83631cd
Signed-off-by: xiaoyao <xiaoyao@rock-chips.com>

ARM64: configs: update rockchip_linux_defconfig by savedefconfig

Change-Id: I82e2827c8356e0577bd6426d7275339ef6a83152
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>

arm64: rockchip_defconfig: enable RT5651_TC358749

enable CONFIG_SND_SOC_ROCKCHIP_RT5651_TC358749
for HDMIIn function

Change-Id: I5c77b3f03d75ea1c51a89a2396ff6472554025a5
Signed-off-by: LuoXiaoTan <lxt@rock-chips.com>

ASoC: rt5651: add alc5651 ASRC switch for HDMIIn

Change-Id: I447228656d5ee56b2c4b04c515ad71f34e107ba0
Signed-off-by: LuoXiaoTan <lxt@rock-chips.com>

arm64: dts: rk3399-sapphire: enable isp0 isp1

Enable isp0 & isp1 for HDMIIn video function

Change-Id: I1f46c413f198acdce7a08702c42f0142d6eabfd6
Signed-off-by: LuoXiaoTan <lxt@rock-chips.com>

arm64: dts: rk3399-sapphire: add HDMIIn sound dev

sable rt5651 simple-audio-card and we will write
a machine driver for rt5651 tc358749x HDMIIn function.
And add rt5651-tc358749x-sound for HDMIIn function

Change-Id: I983fa9171bfa1fb3bf0ab492354e471046c08e93
Signed-off-by: LuoXiaoTan <lxt@rock-chips.com>

arm64: dts: rk3399-sapphire: add tc358749x device

add tc358749x i2c dev & pin control for HDMIIn function
base on board (RK_EXCAVATOR_MAIN_V12_2016_11_11_FZB)

Change-Id: I5548a31d78e4d7cc9ecae0dc89f2ee2dcd0e75b4
Signed-off-by: LuoXiaoTan <lxt@rock-chips.com>

arm64: dts: rk3399-sapphire: add iomux for hdmiin

add pinctrl for tc358749x power control

Change-Id: I4e72b936fb7190791f13d83799155f80e257a117
Signed-off-by: LuoXiaoTan <lxt@rock-chips.com>

Documentation: DT: ASoC: add toshiba tc358749x

Change-Id: Id03458c15f5f87aeeacb21645d37bb95978ee57f
Signed-off-by: LuoXiaoTan <lxt@rock-chips.com>

Documentation: DT: ASoC: add for rockchip HDMIIn

Change-Id: I984999e66ae24919335b2aef5c732022e78c7e47
Signed-off-by: LuoXiaoTan <lxt@rock-chips.com>

arm64: dts: rk3399-box: compatible for rev2 board which cpu_b's vdd gpio is different

Change-Id: Ie7088b526a1a384435136933a5f57c957e2bb5b0
Signed-off-by: buluess.li <buluess.li@rock-chips.com>

arm64: rockchip_defconfig: enable TCP SYN_COOKIES

solve some vst video apk can't play video with kmsg:
"TCP: request_sock_TCP: Possible SYN flooding on port 9000. Dropping request.  Check SNMP counters."

Change-Id: I4fc94307195464c8e8180217eccb9a590eb3c5b6
Signed-off-by: huweiguo <hwg@rock-chips.com>

ARM64: dts: rk3399-android: change i2s2 bclk to 128fs for hdmi

Change-Id: I6345cf044aaf5d617f4a7cd77eca98c473eb9195
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>

drm: bridge/dw-hdmi: add support for hdmi bitstream audio

Change-Id: Ib1f6c5dba6451f3fbb029b5472dbfbf5694cff68
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>

ASoC: codec: hdmi-codec: add support for audio mode config

Change-Id: I4813e6204fee894ef4f40b3e3b768a1ad94d0a29
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>

ASoC: rockchip: hdmi_dp: add support for 192k

Change-Id: Ib50106f9c44ef86f2e20cf2b2206b54c8c966a29
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>

ASoC: rockchip: i2s: increase dma maxburst to 16

Change-Id: I84898fced94141b29e88f2e8f8f9328881090c25
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>

drm: bridge: dw-hdmi: optimize edid reading process

1.change SDA high level holding time to 3us.
2.when plug in,add timer to avoid unstable state.

Change-Id: Idc6faec710137ac9f8e589d75cbc1b85f7a45faf
Signed-off-by: algea.cao <algea.cao@rock-chips.com>

arm64: dts: rk3399-mid: rk818 enabled boost_otg fix ota vcc5v poweroff when susppend

Change-Id: I2d11a76a21d7a8fe18124312c68b744f4364f4fd
Signed-off-by: Wu Liangqing <wlq@rock-chips.com>

arm64: dts: rk3368: rk818 enabled boost_otg fix ota vcc5v poweroff when susppend

Change-Id: I0626a47da5487d34c0701d2b21cfab5b9b3fb425
Signed-off-by: Wu Liangqing <wlq@rock-chips.com>

arm64: dts: rockchip: add L2 cache node for rk3368

This patch adds the L2 cache topology on RK3368.
RK3368 has two clusters, each cluster has its own L2 cache.

Change-Id: Ibee5a39889d4924e439c9b0c249df052f63e9242
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>

arm64: dts: rockchip: remove unneeded idle-states for rk3368

ATF and Linux support system suspend, so we don't need define
idle-states to support suspend. RK3368 don't support any
idle state other then WFI. Just remove it.

Change-Id: Ifa95862b4998287560cd2214ff6b5763a9d6ce02
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>

arm: configs: enable some touchscreen driver

Change-Id: I44cc2ef0a230dea6c60cddf2e6aa7195985468ed
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>

arm: configs: linux: enable wifi load driver when boot kernel

if we don't enable it, driver init order might be wrong

Change-Id: I0d75b6fcdb762a77f8c27111da642cdba255fc4e
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>

drm/sysfs: fix up memory leak problem

Change-Id: I2b4617412b0d5b2897c3cce2ef612a11a9762ba2
Signed-off-by: algea.cao <algea.cao@rock-chips.com>

arm: dts: rockchip: update thermal config for rk3288

add cpus' dynamic power coefficient. rename the thermal zone's config
and make it more readable. update temperature pooling interval and
make the temperature control more effective.

Change-Id: I75d21601b7e3f41a32d10bbcbb1fa9b47ed7da0f
Signed-off-by: Rocky Hao <rocky.hao@rock-chips.com>

arm64: dts: rockchip: add tsadc's working clock rate for rk3288

add tsadc's working clock rate for rk3288. if not set, tsadc
will work at the default rate of 1k hz.

Change-Id: I1b26351c3fb97f5ceb4657c2356c2f5649ad140c
Signed-off-by: Rocky Hao <rocky.hao@rock-chips.com>

ARM64: dts: rockchip: rk3399: set dummy_cpll and dummy_vpll as fixed clk

to fix up :
[    0.000000] clk: couldn't get clock 4 for /clock-controller@ff760000
[    0.000000] rockchip_clk_of_add_provider: could not register clk provider
The cause of the error:
struct clk *__clk_create_clk(struct clk_hw *hw, const char *dev_id,
     const char *con_id, bool with_orphans)
{
/* This is to allow this function to be chained to others */
if (!hw || IS_ERR(hw))
return (struct clk *) hw;

if (hw->core->orphan && !with_orphans)
return ERR_PTR(-EPROBE_DEFER);

return clk_hw_create_clk(hw, dev_id, con_id);
}
if clk is orphan and not have the with_orphans flag, it will
register clk provider failed.

Change-Id: I87ca9ec087611a5425545bfc857b09d8438218b5
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

clk: defer clk_gets on orphan clocks

Orphan clocks or children of orphan clocks don't have rate information at
all and can produce strange results if they're allowed to be used and the
parent becomes available later on.

This change, based on one from Stephen Boyd, defers __clk_create_clk()
calls on orphan clocks in all regular cases.

One special case that gets handled, is accessing such orphan clocks when
handling assigned-clocks configurations. In the boot-defaults it may be
the case that a clock is connected to an orphan parent which then might
be needed to get reparented to an actually usable clock using
assigned-clock-parents. In this case even orphaned clocks should be
usable, but only for the set-parent case.

The added of_clk_get_from_provider_with_orphans() is only available
to ccf internal parts to prevent abuse.

(am from https://patchwork.kernel.org/patch/7690221/)

Change-Id: I2e603dab191fa8a431adebad1f9d482d52b7deeb
Signed-off-by: Heiko Stuebner <heiko.stuebner@collabora.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

arm64: dts: rockchip: rk3368: revert xin32k use the fixed clk

This reverts commit 61e585b9ef7f0aa9bce9f004771becda795aa563.

Change-Id: Id46aa6bf2822c1b9e53de544b349b42645cb6a5a
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

arm64: dts: rockchip: add gsl3680 and mpu6050 for RK3399 Firefly Board

Change-Id: I8e6f4802d4c1b10873c655cc620e6d7be47efee7
Signed-off-by: hero.huang <hero.huang@rock-chips.com>